Fujitsu Series 3 Manual

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[bit 12] WSEL: Wait selection bit 
 If DMA mode is disabled (SSR:DMA=0), this bit selects a generation time of interrupt before or after 
acknowledgement (INT=1) an d selects to wait the I2C bus or not. 

 If DMA mode is enabled (SSR:DMA=1), this bit sel ects a generation time of interrupt before or after 
acknowledgement (INT=1,  and SSR:TBI=1 for transmission or SSR:RDRF=1 for reception) and 
selects to wait the I
2C bus or not. 

 The WSEL bit is invalid in the following conditions. 
1.
 An interrupt occurs (INT=1) for the first byte. (*1) 
2.
 The reserved address is detected (IBSR:FBT=1, IBSR:RSA=1). 
3.
 The NACK response is detected during FIFO data transmission (FCR0:FE=1, IBSR:RACK=1,  ACT=1). (*2) 
4.
 The receive FIFO is filled with data during FIFO reception. 
*1) The first byte indicates data after the (iteration) start condition. 
*2) NACK response: The SDA bit of I
2C bus is HIGH during acknowledgement. 
 
Bit Description 
0  Waits (9 bits) after acknowledgement. 
1 Waits (8 bits) after data transmission or reception. 
 
[bit 11] CNDE: Condition detection interrupt enable bit 
This bit enables an interrupt if a stop condition or an  iteration start condition is detected in master or slave 
mode (ACT=1). An interrupt occurs if  the RSC or SPC bit of IBSR register is 1 and if this bit is set to 
1. 
Bit Description 
0  Disables an interrupt due to the iteration start or stop condition. 
1  Enables an interrupt due to the iteration start or stop condition. 
 
[bit 10] INTE: Interrupt enable bit 
This bit enables an interrupt (INT=1) due to a data  transmission or bus error in master or slave mode. 
Bit Description 
0 Disables an interrupt. 
1  Enables an interrupt. 
 
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[bit 9] BER: Bus error flag bit 
This bit indicates that an error has been detected on the I2C bus. 
The BER bit is set when:  1.
 The start or stop condition is detected during transmission of the first byte. (*1) 
2.
 The (iteration) start condition or the stop condition is  detected at bit 2 to 9 (acknowledgement) of data 
after the 2nd or subsequent byte. 
 
The BER bit is reset when: 
1.
 The INT bit is set to 0 if BER=1. 
2.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
*1) The first byte indicates data after the (iteration) start condition. 
 
Bit Description 
0 No  error 
1 An error was detected. 
 
 
Check this  b

it state if the interrupt flag (INT bit) is  1. If it is 1, the normal data tran
 smission and 
reception fail. Retransmit the data. 
 
[bit 8] INT: interrupt flag bit 
The interrupt flag bit is set to 1 after 8 or 9 bits  (ACK) of data have been transmitted or when a bus error 
has occurred in master or slave mode. During operation ot her than bus error, if the INT bit is set to 1, the 
SCL flag is set to LOW. If the INT bit is set to 0, the SCL flag is released from the LOW state. 
The INT bit is set when: 
 
 1.
 The reserved address is detected in the first byte. 
2.
 The WSEL bit is 1 and an arbitration lost is detected in the 2nd or subsequent byte. 
 
 
1.
 If DMA mode is disabled (SSR:DMA=0), WSEL bit is 1, master mode is selected, and the 
SSR:TDRE bit is 1 in the 2nd or subsequent byte. 
2.
 If DMA mode is disabled (SSR:DMA=0), WSEL bit  is 1, slave mode is selected, the receive 
FIFO is disabled, and the SSR:TDRE bit is 1 in the 2nd or subsequent byte. 
3.
 If DMA mode is disabled (SSR:DMA=0), WSEL bit  is 1, the slave mode transmission is selected, 
and the SSR:TDRE bit is 1 in the 2nd or subsequent byte. 
4.
 If DMA mode is disabled (SSR:DMA=0), WSEL bit  is 1, the receive FIFO is disabled, and the 
slave mode reception is selected. 
 
 
1.
 If DMA mode is enabled (SSR:DMA=1), WSEL bit is  1, master mode is selected , the SSR:TBI 
bit is 1 in the 2nd or subsequent  byte, and the INT bit is set to 1. 
 
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  1.
 An arbitration lost is detected in the first byte. 
2.
 The NACK signal is received during the time othe r than stop condition output setting (the MSS bit 
is set to 0 during the master mode operation). 
3.
 The WSEL bit is 0 and an arbitration lost is detected in the 2nd or subsequent byte. 
4.
 The reserved address is not detected in the 1st byte, and data is fo und in the receive FIFO when the 
receive FIFO is enabled and data is received in master or slave mode (IBSR:TRX=0). 
 
 
1.
 If DMA mode is disabled (SSR:DMA=0), the reserved address is not detected in the 1st byte, and 
the SSR:TDRE bit is 1 when data is transm itted (IBSR:TRX=1) in master or slave mode. 
2.
 If DMA mode is disabled (SSR:DMA=0), the reserved address is not detected in the 1st byte, and 
the SSR:TDRE bit is 1 when the receive FIFO  is disabled for data reception (IBSR:TRX=0) in 
master or slave mode. 
3.
 If DMA mode is disabled (SSR:DMA=0), WSEL b it is 0, and the SSR:TDRE bit is 1 in the 
2nd or subsequent byte during the master mode operation. 
4.
 If DMA mode is disabled (SSR:DMA=0), WSEL b it is 0, and the SSR:TDRE bit is 1 in the 
2nd or subsequent byte during the slave mode transmission. 
5.
 If DMA mode is disabled (SSR:DMA=0), WSEL bit  is 0, the receive FIFO is disabled, and the 
slave mode reception is selected. However, if the reserved address is detected in the 1st byte during 
the slave mode reception, no interrupt is generated by bit 9. 
6.
 If DMA mode is disabled (SSR:DMA=0), the receive  FIFO is enabled, data is received in slave 
mode, and the receive FIFO is filled with data. 
 
 
1.
 If DMA mode is enabled (SSR:DMA=1), the reserved address is not detected in the 1st byte, and 
the SSR:TDRE bit is 1 when data is transmitted (IBSR:TRX=1) in slave mode. 
2.
 If DMA mode is enabled (SSR:DMA=1), the reserved address is not detected in the 1st byte, and 
the SSR:TDRE bit is 1 when the receive FIFO  is disabled for data reception (IBSR:TRX=0) in 
slave mode. 
3.
 If DMA mode is enabled (SSR:DMA=1), WSEL bit is  0, the SSR:TBI bit is 1 in the 2nd or 
subsequent byte during the master mode operation, and the INT bit is set to 1. 
 
 
1.
 bus error is detected. 
 
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The INT bit is reset when: 1.
 The INT bit is set to 0. 
2.
 The INT bit is 1 and the ACT bit is 1, the MSS bit is set to 0. 
3.
 The INT bit is 1 and the ACT bit is 1, the SCC bit is set to 1. 
 
If the DMA mode is disabled (SSR:DMA=0), it is invalid to set the INT bit to 1. 
Description Bit  During writing During reading 
0  Clears the INT bit.  Does not issue an interrupt request. 
1  No effect  Issues an interrupt request. 
 
 

 When DMA mode is enabled (SSR:DMA=1) and the SSR:TBI bit is 1 in the 2nd or subsequent byte 
during the master mode operation, a status interrupt (SIRQ=1) is not generated even when the INT bit 
is set to 1. 

 When DMA is enabled (SSR:DMA=1), the SSR:TBI bit  is 1 and the IBCR:INT bit is 0, follow the 
steps below to issue the iteration start condition.  1.
 Set the IBCR:INT bit to 1. 
2.
 Check that the IBCR:INT bit is set to 1. 
3.
 Write the slave address in the TDR. 
4.
 Set the IBCR:SCC bit to 1. 

 If the INT flag is changed from 1 to 0, the I2C bus is released from waiting. 

 If the ISMK:EN bit is set to 0, the SSR:RDRF and IN T bits may be set to 1 in certain receive timing. 
If so, read the received data and clear the INT bit. 

 When a read-modify-write instruction is issued, 1 is read. 

 If the receive FIFO is enabled, the INT bit is not set to 1 even when th e receive FIFO is filled with data 
during the master mode reception. 

 Set this bit to 1 when the start condition is issued (IBCR:MSS=1). 
 
 
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5.2.  Serial Mode Register (SMR) 
The Serial Mode Register (SMR) is used to set an operation mode, and to enable or disable 
the transmit/receive interrupt. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SCR) MD2 MD1 MD0 WUCRRIE TIE ITST1 ITST0
Attribute     R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7:5] MD2, MD1, MD0: operation mode set bits 
These bits set an operation mode. 
0b000: Sets operation mode 0 (async normal mode). 
0b001: Sets operation mode 1 (async multiprocessor mode). 
0b010: Sets operation mode 2 (clock sync mode). 
0b011: Sets operation mode 3 (LIN communication mode). 
0b100: Sets operation mode 4 (I
2C mode). 
This section explains the registers and their operation in operation mode 4 (I
2C mode). 
Bit 7  Bit 6Bit 5  Description 
0 0 0 Operation mode 0 (async normal mode) 
0  0 1 Operation mode 1 (async multiprocessor mode) 
0  1 0 Operation mode 2 (clock sync mode) 
0  1 1 Operation mode 3 (LIN communication mode) 
1 0 0  Operation mode 4 (I2C mode) 
* This section explains the registers in operation mode 4. 
 

 Any bit setting other than above is inhibited. 

 To switch the current operation mode, disable the I2C (ISMK:EN=0) and change the operation mode. 

 After the operation mode has been switched, set each register correctly. 
 
[bit 4] WUCR: Wake-up control bit 
Selects a pin to be used for an external interrupt. 
If this bit is set to 0, the INT pin is used for an external interrupt. 
If this bit is set to 1, the SDA or SCL pin is used for an external interrupt. 
Bit Description 
0  Disables the Wake-up function. 
1  Enables the Wake-up function. 
 
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[bit 3] RIE: Receive interrupt enable bit 
 This bit enables or disables an output of receive interrupt request to the CPU. 

 If the RIE bit and the receive data flag bit (SSR:RDRF) are 1, or if any of erro r flag bits (SSR:ORE) is 
1, a receive interrupt request is output. 
 
Bit Description 
0  Disables the receive interrupt. 
1  Enables the receive interrupt. 
 
 
To recei ve 

data using the INT bit of I
2C Bus Control Register (IBCR) when DMA mode is disabled 
(SSR:DMA=0), set this bit to 0. 
 
[bit 2] TIE: Transmit interrupt enable bit 
 This bit enables or disables an output of Transmit Interrupt Request to the CPU. 

 If the TIE and SSR:TDRE bits are 1, a Transmit Interrupt Request is output. 
 
Bit Description 
0  Disables the transmit interrupt. 
1  Enables the transmit interrupt. 
 
 
To tran sm

it data using the INT bit of I
2C Bus Control Register (IBCR) when DMA mode is disabled 
(SSR:DMA=0), set this bit to 0. 
 
[bit 1:0] ITST1, ITST0: I2C test bits 
They are I2C Test bits. 
They must always be set to 0. 
Bit 1:0  Description 
0 Disables  the I2C test. 
1 Enables  the I2C test. 
 
 
If this  b

it is set to 1, the I
2C test is executed. 
  
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5.3. I2C Bus Status Register (IBSR) 
The I2C Bus Status Register (IBSR) shows the iteration start, acknowledgement, data 
direction, arbitration lost, stop condition, I2C bus status, and bus error detection. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SSR) FBT RACKRSA TRX AL RSC SPC BB 
Attribute      R R R  R R R/W R/W  R 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] FBT: First byte bit 
This bit indicates the first byte. 
The FBT bit is set when: 
1.
 The (iteration) start condition is detected. 
 
The FBT bit is cleared when: 
1.
 The second byte is sent or received. 
2.
 The stop condition is detected. 
3.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
4.
 A bus error is detected (IBCR:BER bit=1). 
 
Bit Description 
0  Other than 1st byte 
1 The 1st byte is being sent or received. 
 
[bit 6] RACK: Acknowledge flag bit 
This bit shows acknowledgement being received in the 1st byte or in master or slave mode. 
The RACK bit is updated when:  1.
 Acknowledged in the 1st byte. 
2.
 Data is acknowledged in master or slave mode. 
 
The RACK bit is cleared (RACK bit=0) when: 
1.
 The (iteration) start condition is detected. 
2.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
3.
 A bus error is detected (IBCR:BER bit=1). 
 
Bit Description 
0 LOW  is received. 
1  HIGH is received. 
 
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[bit 5] RSA: Reserved address detection bit 
This bit shows that the reserved address has been detected. 
The RSA bit is set (RSA=1) when:  1.
 The 1st byte is 0000xxxx or 1111xxxx. where, x can be 0 or 1. 
 
The RSA bit is reset (RSA=0) when: 
1.
 The (iteration) start condition is detected. 
2.
 The stop condition is detected. 
3.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
4.
 A bus error is detected (IBCR:BER bit=1). 
 
If the RSA bit is set to 1 in the 1st byte, the interrupt flag (IBCR:INT) is set to  1 and the SCL flag is set 
to L at the falling edge of SCL (bit 8) of the 1st byte  regardless of FIFO enable or disable state. To read 
the received data and start the slave mode operation during this time , set the IBCR:ACKE bit to 1 and 
clear the interrupt flag (IBCR:INT) to 0. If the TRX bit  is 0 after that, data is received in slave mode. To 
stop the data reception, set the IBCR:ACKE b it to 0. No data is received after that. 
Bit Description 
0 The reserved address is not detected. 
1  The reserved address is detected. 
 
 

 If the IBCR:ACKE bit is set to 0 during data tran sfer, this IBCR:ACKE bit cannot be set to 1 until 
the stop condition or the iteration start condition is detected. 

 If the slave mode transmission is detected during an interrupt by reserved address detection and if the 
receive FIFO is enabled, an ACK response is returned. In this case, disable the receive FIFO and set the 
IBCR:ACKE bit to 0. 
 
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[bit 4] TRX: Data direction bit 
This bit indicates the data transmission direction. 
The TRX bit is set when: 1.
 The (iteration) start condition is sent in master mode. 
2.
 Bit 8 of the 1st byte is 1 in slave mode (in the slave mode transmission direction). 
 
The TRX bit is reset when: 
1.
 An arbitration lost occurs (AL=1). 
2.
 Bit 8 of the 1st byte is 0 in slave m ode (in the slave mode reception direction). 
3.
 Bit 8 of the 1st byte is 1 in master mode  (in the master mode reception direction). 
4.
 The stop condition is detected. 
5.
 The (iteration) start condition is detected in any mode other than master mode. 
6.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
7.
 A bus error is detected (IBCR:BER bit=1). 
 
Bit Description 
0 Receive  direction 
1 Transmission  direction 
 
[bit3] AL: Arbitration  lost  bit 
This bit indicates an arbitration lost. 
The AL bit is set when: 
1.
 The output data does not match th e receive data in master mode. 
2.
 The IBCR:MSS bit is set to 1 but the slave mode operation is selected. 
3.
 The iteration start condition is detected by bit 1 of the 2nd or subsequent byte data in master mode. 
4.
 The stop condition is detected by bit 1 of the 2nd or subsequent byte data in master mode. 
5.
 The iteration start condition cannot be generated in master mode. 
6.
 The stop condition cannot be generated in master mode. 
 
The AL bit is reset when: 
1.
 The IBCR:MSS bit is set to 1. 
2.
 The IBCR:INT bit is set to 0. 
3.
 The SPC bit is set to 0 when both AL and SPC bits are 1. 
4.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
5.
 A bus error is detected (IBCR:BER bit=1). 
 
Bit Description 
0  No arbitration lost has occurred. 
1 An arbitration lost has occurred. 
 
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[bit 2] RSC: Iteration start condition check bit 
This bit shows that an iteration start condition is detected in master or slave mode. 
The RSC bit is set when: 1.
 When an iteration start condition is detected after acknowledgement, during the master or slave mode operation. 
 
The RSC bit is reset when: 
1.
 The RSC bit is set to 0. 
2.
 The IBCR:MSS bit is set to 1. 
3.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
 
It is invalid to set this bit to 1. 
Bit Description 
0  No iteration start condition has been detected. 
1 An iteration start condition has been detected. 
 
 

 If no acknowledgement response is sent while data is  received in slave mode due to the reserved address 
being detected, slave mode is released. In this case, this bit is not set to 1 even if the next iteration start 
condition is detected. 

 When a read-modify-write instruction is issued, 1 is read. 
 
[bit 1] SPC: Stop condition check bit 
This bit shows that a stop condition is detected in master or slave mode. 
The SPC bit is set when: 
1.
 The stop condition is detected in the master or slave mode operation. 
2.
 In master mode, the stop condition has occurred and, therefore, an arbitration lost has occurred. 
 
The SPC bit is reset when: 
1.
 This bit is set to 0. 
2.
 The IBCR:MSS bit is set to 1. 
3.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
 
It is invalid to set this bit to 1. 
Bit Description 
0  No stop condition is detected. 
Master 
mode  An arbitration lost has occurred when the stop condition is detected or when it is 
output. 
1 
Slave mode  The stop condition is detected. 
 
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