Fujitsu Series 3 Manual

							 
4. Registers 
 
[bit 8] CDCIE: Count inversion interrupt enable bit This bit is used to control whether or not to issue an interrupt notification to the CPU when the count 
inversion interrupt request fl ag (CDCF) is set to 1. 
When this bit is set to 1, an interrupt is generated  if the count direction of the position counter is inverted 
(CDCF=1). 
Bit Description 
0 Interrupt disabled 
1 Interrupt enabled 
 
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CHAPTER  17: Quad  Position  & Revolution  Counter 
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4. Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Quad Position & Revolution Counter 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  39  
4.9.  QPRC Maximum Position Register(QMPR) 
The QPRC Maximum Position Register (QMPR) is used to specify the maximum value of the 
position counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field QMPR[15:0] 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/WR/WR/WR/WR/W R/W R/W R/W R/W
Initial 
value  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 
 
[bit 15:0] QMPR:    When the position counter is counted up, a position c ounter overflow is detected (QICR:OFDF=1) if the 
set value of the QPRC Maximum Position Register (QMPR) matches the value of the position counter. 
When the position counter is counted down, the set value of the QPRC Maximum Position Register 
(QMPR) is reloaded to the position counter if a pos ition counter underflow is detected (QICR:UFDF=1). 
 
 
Do not access the QPRC Maximum Position Register  (QMPR) with a byte access instruction. 
 
 
CHAPTER  17: Quad  Position  & Revolution  Counter 
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1. Configuration 
 
CHAPTER: A/D Converter 
This chapter explains the functions and operations of the A/D converter. 
 
1.
 Configuration 
2. Functions and Operations 
3. Notes 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFADCTOP-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-1: A/D Converter 
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1. Configuration 
 
1. Configuration 
A/D converter converts analog input voltage from an external pin to a digital value. 
 A/D converter configuration 
  3 units of A/D converters with 10-bit resolution or 12-bit resolution are installed. 
   Any channel can be selected to any unit from 16 channels of analog input. 
   The following triggers can be selected as  an activation trigger for A/D conversion. 
   Priority conversion activation trigger 
Trigger input from an external pin 
Timer trigger input (base timer or multifunction timer) 
Software activation 
   Scan conversion activation trigger 
Timer trigger input (base timer or multifunction timer) 
Software activation 
Figure 1-1  shows a connection diagram of the A/D converter with the related circuits. 
Figure 1-1 Block diagram of the A/D converter with the related circuits 
 
I/O port
selection circuit
ADTG_0Analog Selector
AN00
AN01
AN02
AN03
AN04
AN15
ADTG_1
ADTG_2
ADTG_8
Base timer ch. 0 to 7 output (8 triggers)
ADC
unit0
Scan conversion 
timer activation
Priority conversion 
external trigger activation
Priority conversion  timer activation
SEL ADC0 scan activation in multifunction timer unit0
SEL
ADC
unit1
SEL
SEL
ADC
unit2
SEL
SEL
Analog input pin
A/D activation trigger  input pin  ADC0 scan activation in multifunction timer unit1
Scan conversion 
timer activation
Priority conversion 
external trigger activation Priority conversion 
timer activation
Scan conversion  timer activation
Priority conversion 
external trigger activation Priority conversion 
timer activation
Base timer ch. 0 to 7 output (8 triggers)
 ADC0 priority activation in multifunction timer unit0
 ADC0 priority activation in multifunction timer unit1
Base timer ch. 0 to 7 output (8 triggers) ADC1 scan activation 
in multifunction timer unit0
Base timer ch. 0 to 7 output (8 triggers)  ADC1 scan activation 
in multifunction timer unit1
 ADC1 priority activation  in multifunction timer unit0
 ADC1 priority activation 
in multifunction timer unit1
Base timer ch. 0 to 7 output (8 triggers)  ADC2 scan activation 
in multifunction timer unit0
Base timer ch. 0 to 7 output (8 triggers)  ADC2 scan activation 
in multifunction timer unit1
 ADC2 priority activation  in multifunction timer unit0
 ADC2 priority activation 
in multifunction timer unit1
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-1: A/D Converter 
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2. Functions and Operations 
 
2.  Functions and Operations 
See descriptions of the following related chapters for functions and operations of the A/D 
converter. 
 10-bit A/D converter operation 
See the chapter of 10-bit A/D Converter for  conversion operations of 10-bit A/D converter. 
 10-bit A/D timer trig ger select operation 
See the chapter of A/D Timer Trigger Selection fo r operations of 10-bit A/D converter timer trigger 
selection. 
  12-bit A/D converter operation 
See the chapter of 12-bit A/D Converter for  conversion operations of 12-bit A/D converter. 
 12-bit A/D timer trig ger select operation 
See the chapter of A/D Timer Trigger Selection fo r operations of 12-bit A/D converter timer trigger 
selection. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-1: A/D Converter 
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3. Notes 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: A/D  Converter 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  5 
3. Notes 
This section shows the notes. 
  Notes on 10-bit A/D converter 
 
  Simultaneous A/D conversion of 3 channels is possible because 3 units of A/D converters are installed. 
Do not select the same input channel with the multiple units. 
 
   Some channels of an analog input cannot be used for certain models. Do not change the selection 
registers (SCIS0, SCIS1, SCIS2, and SCIS3) and the sampling time selection registers (ADSS0, ADSS1, 
ADSS2, and ADSS3) for the channels which cannot be used from their initial values. 
 
   In this series, P1A[2:0] of the priority conversion input selection register (PCIS) should be selected for 
an analog input channel during priority conversion. Always write 0 to ESCE bit of the priority 
conversion control register (PCCR) of the 10-bit A/D converter. 
 
   DMA transfer using the A/D interrupt request generation of this series supports only DMA transfer using 
generation of a scan conversion interrupt request. DMA transfer using a priority conversion interrupt 
request is not supported. 
 
  Notes on 12-bit A/D converter 
 
  Simultaneous A/D conversion of 3 channels is possible because 3 units of A/D converters are installed. 
Do not select the same input channel with the multiple units. 
 
   Some channels of an analog input cannot be used for certain models. Do not change the selection 
registers (SCIS0, SCIS1, SCIS2, and SCIS3) and the sampling time selection registers (ADSS0, ADSS1, 
ADSS2, and ADSS3) for the channels which cannot be used from their initial values. 
 
   In this series, P1A[2:0] of the priority conversion input selection register (PCIS) should be selected for 
an analog input channel during priority conversion. Always write 0 to ESCE bit of the priority 
conversion control register (PCCR) of the 10-bit A/D converter. 
 
   DMA transfer using the A/D interrupt request generation of this series supports only DMA transfer using 
generation of a scan conversion interrupt request. DMA transfer using a priority conversion interrupt 
request is not supported. 
 
CHAPTER  18-1: A/D Converter 
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1. Overview 
 
Chapter: 10-bit A/D Converter 
This chapter explains the functions and operations of the 10-bit A/D converter. 
 
1.
 Overview 
2. Configuration 
3. Explanation of Operations 
4. Setup procedure examples 
5. Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BF10BADC-E01.2_FG65-J03.0 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-2: 10-bit  A/D Converter 
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1. Overview 
 
1. Overview 
The 10-bit A/D converter is a function that converts analog input voltages into 10-bit digital 
values using a type of the RC Successive Approximation Register. 
 Features of the 10-bit A/D converter 
  10-bit resolution 
   Converter using a type of RC Successive Approximation Register with sample and hold circuits 
   Conversion time of 1.2  s (at a peripheral clock frequency of 30 MHz) 
   Two sampling times selectable for each input channel 
   Scan conversion operation:   
Multiple analog inputs can be selected from multiple channels. 
Start factors are software and timers. 
Repeat mode is available. 
   Priority conversion operation:   
Even during scan operation, if a start factor of priority conversion o ccurs, it is possible to interrupt the 
ongoing scan conversion and perform conversion with high priority (There are two priority levels: 1 and 
2. Priority level 1 is higher than priority level 2.). 
Start factors are software and timers (priority le vel 2), and external triggers (priority level 1). 
   FIFO function:   
Sixteen FIFO stages for scan conver sion and four FIFO stages for priority conversion are incorporated. 
An interrupt is generated when data is wr itten in the specified count of FIFO stages. 
   Changeable A/D conversion data placement (selectable  between shift to the MSB side and shift to LSB 
side) 
   The A/D conversion result comparison function is available. 
   There are four interrupt sources as follows: 
1. Scan conversion FIFO stage count interrupt 
2.  Priority conversion FIFO stage count interrupt 
3.  FIFO overrun interrupt (for both scan and priority conversion processes) 
4.  A/D conversion result comparison interrupt 
   DMA transfer triggered by an interrupt request 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-2: 10-bit  A/D Converter 
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2. Configuration 
 
2. Configuration 
This section provides the configuration of the 10-bit A/D converter. 
 10-bit A/D converter block diagram 
Figure 2-1 10-bit A/D converter block diagram 
 
Control unit
A/D converter
Channel & status control unit
Peripheral buses
Buffer
Scan conversion FIFO, 16 
stages  
Priority conversion FIFO, 4  stages
D/A converter  
Comparator  
Sample 
& 
holdAnalog input n
Analog input n-1 ･
･
･
･
Analog input 3
Analog input 2
Analog input 1
Analog input 0
A/D conversion result 
comparison interrupt
FIFO overrun interrupt
Scan FIFO interrupt
Priority FIFO interruptTimer trigger
External trigger pin
Ｍ  
Ｐ  
Ｘ  
  
 Input impedance 
The sampling circuit of the A/D converter is shown as an equivalent circuit in  Figure 2-2. Refer to the 
Electrical Characteristics in the data sheet to make  su
re that the external impedance Rext should be 
selected not to exceed  the sampling time. 
Figure 2-2 Input impedance equivalence circuit diagram 
 
Analog 
signal 
source Rext
Analog SWRin
Cin ADC
LSI
  
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-2: 10-bit  A/D Converter 
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3. Explanation of Operations 
 
3.  Explanation of Operations 
This chapter explains the operations of the 10-bit A/D converter. 
 
3.1 A/D conversion operation 
3.2  FIFO operations 
3.3  A/D comparison function 
3.4  Starting DMA 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-2: 10-bit  A/D Converter 
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