Fujitsu Series 3 Manual

							 
7. UART (Async Serial Interface) Registers 
 
[bit 8] FSEL: FIFO select bit This bit selects the tr ansmit or receive FIFO. 
If set to 0, transmit FIFO is assigned FIFO 1, and the receive FIFO is assigned FIFO2. 
If set to 1, transmit FIFO is assigned FIFO 2, and the receive FIFO is assigned FIFO1. 
Bit Description 
0 Transmit FIFO:FIFO1; Receive FIFO:FIFO2 
1 Transmit  FIFO:FIFO2; Receive FIFO:FIFO1 
 
 
  This bit  is 

not cleared by the  FIFO Reset (FCR0:FCL2, FCL1 =1). 
   T

o change this bit state, first disable the FIFO operation (FCR:FE2, FE1=0). 
 
 
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7. UART (Async Serial Interface) Registers 
 
7.8.  FIFO Control Register 0 (FCR0) 
The FIFO Control Register 0 (FCR0) is used to enable/disable the FIFO operation, reset FIFO, 
save the read pointer, and set the data re-transmission. 
 bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (FCR1) - FLSTFLD FSETFCL2FCL1 FE2 FE1 
Attribute      -  R R/W  R/W R/W R/W  R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] Unused bit  When read, always 0 is read. 
When written, always set this bit to 0. 
 
[bit 6] FLST: FIFO re-transmit data lost flag bit  This bit shows that the re-transmit data of transmit FIFO has been lost. 
The FLST bit is set when: 
  Data is written (overwritten) in th e FIFO buffer when the FLSTE bit  of FIFO Control Register 1 (FCR1) 
is 1 and the write pointer for tr ansmit FIFO matches the read pointer which has been saved by the 
FSET bit.   
 
The FLST bit is reset when: 
   FIFO is reset (FCL bit is set to 1). 
   The FSET bit is set to 1. 
 
If this bit is set to 1, the data identified by the  read pointer (saved by the FSET bit) is overwritten. 
Therefore, the FLD bit cannot set the data re-transmission even if an error has occurr ed. If this bit is set to 
1 and if you wish to re-transmit data, first reset FIFO. Then, write data in the FIFO buffer again. 
Bit Description 
0  No Data Lost has occurred. 
1  Data Lost has occurred. 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 5] FLD: FIFO pointer reload bit This bit reloads the data, being saved in transmit FIFO by  the FSET bit, to the reload pointer. This bit can be 
used to re-transmit data after a communication error or others have occurred. 
When the re-transmission setting has finished, this bit is set to 0. 
Bit Description 
0 Not  reloaded 
1 Reloaded 
 
 
  If this  b

it is 1, data is being reloaded in the read  point
 er. Therefore, data writing except for FIFO reset 
is disabled. 
   When FIFO is enabled or when data is being transmitted, this bit cannot be set to 1. 
   After you have set the TIE bit and TBIE bit to 0,  set this bit to 1. After you have enabled transmit 
FIFO, set the SCR:TIE bit and SCR:TBIE bit to 1. 
 
[bit 4] FSET: FIFO pointer save bit  This bit saves the transmit FIFO read pointer. 
If the read pointer value is saved before being transm itted and if the FLST bit is 0, the data can be 
re-transmitted even if a communication error or others have occurred. 
If set to 1, the current read pointer value is saved. 
If set to 0, it has no effect. 
Description Bit  During writing During reading 
0 Not  saved 0 is always read. 
1  FIFO2 is reset. 
 
 
This b it can b

e set to 1 only when the transmit byte count (FBYTE) is 0. 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 3] FCL2: FIFO2 reset bit This bit resets the FIFO2 value. 
If this bit is set to 1, the FIFO2 internal state is initialized. 
Only the FCR1:FLST bit is initialized, and th e other bits of FCR1/0 registers are kept. 
Description Bit 
During writing During reading 
0 No  effect. 
1 FIFO2 is reset.  0 is always read. 
 
 
  Disable the tra n

smission and receptio n first, and then reset FIFO2. 
   Set the tran sm

it FIFO interrupt enable bit to 0 before the execution. 
   The valid data count of the FBYTE2 register is set to 0. 
 
[bit 2] FCL1: FIFO1 reset bit  This bit resets the FIFO1 state. 
If t h

is bit is set to 1, the FIFO1 internal state is initialized. 
Only the FCR1:FLST bit is initialized, and th e other bits of FCR1/0 registers are kept. 
Description Bit 
During writing During reading 
0 No  effect. 
1 FIFO1 is reset.  0 is always read. 
 
 
  Disable the tra n

smission and receptio n first, and then reset FIFO1. 
   Set the tran sm

it FIFO interrupt enable bit to 0 before the execution. 
   The valid data count of the FBYTE1 register is set to 0. 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 1] FE2: FIFO2 operation enable bit This bit enables or disables the FIFO2 operation. 
  To use the FIFO2 operation,  set this bit to 1. 
   If FIFO2 is set as transmit FIFO (FCR1:FSEL=1) and if  data exists in FIFO2 when this bit is set to 1, 
the data transmission starts immediately when th e UART is enabled to transmit data (SCR:TXE=1). 
During this time, set both SCR:TIE bit and SCR:TBIE bit to 0. Then, set this bit to 1 and set both 
SCR:TIE bit and SCR:TBIE bit to 1. 
   If receive FIFO is selected by the FSEL bit and if a r eceive error has occurred, this bit is cleared to 0. 
This bit cannot be set to 1 un til the receive error is cleared. 
   If FIFO2 is used as transmit FIFO, this bit must be  set to 1 or 0 when the transmit buffer is empty 
(SSR:TDRE=1). 
   If FIFO2 is used as receive FIFO, this bit must  be set to 0 when the receive buffer is empty 
(SSR:RDRF=0) and no valid data exists in receive  FIFO (FBYTE2=0) after reception is disabled 
(SCR:RXE=0). 
   If FIFO2 is used as receive FIFO, this bit must  be set to 1 when the receive buffer is empty 
(SSR:RDRF=0) after receptio n is disabled (SCR:RXE=0). 
   The FIFO2 state is held even if the FIFO2 operation is disabled. 
 
Bit Description 
0  Disables the FIFO2 operation. 
1  Enables the FIFO2 operation. 
 
[bit 0] FE1: FIFO1 operation enable bit  This bit enables or disables the FIFO1 operation. 
  To use the FIFO1 operation,  set this bit to 1. 
   When the FIFO1 is set as transmit FI FO (FCR1:FSEL=0) and if data exists  in FIFO1 when this bit is set 
to 1, the data transmission starts immediately wh en the UART is set to enable data transmission 
(SCR:TXE=1). During this time, set both SCR:TIE bit an d SCR:TBIE bit to 0. Then, set this bit to 1 
and set both TIE bit and SCR:TBIE bit to 1. 
   If receive FIFO is selected by the FSEL bit and if a r eceive error has occurred, this bit is cleared to 0. 
This bit cannot be set to 1 un til the receive error is cleared. 
   If FIFO1 is used as transmit FIFO, this bit must be  set to 1 or 0 when the transmit buffer is empty 
(SSR:TDRE=1). 
   If FIFO1 is used as receive FIFO, this bit must  be set to 0 when the receive buffer is empty 
(SSR:RDRF=0) and no valid data exists in receive  FIFO (FBYTE2=0) after reception is disabled 
(SCR:RXE=0). 
   If FIFO1 is used as receive FIFO, this bit must  be set to 1 when the receive buffer is empty 
(SSR:RDRF=0) after receptio n is disabled (SCR:RXE=0). 
   The FIFO1 state is held even if the FIFO1 operation is disabled. 
 
Bit Description 
0  Disables the FIFO1 operation. 
1  Enables the FIFO1 operation. 
 
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7. UART (Async Serial Interface) Registers 
 
7.9.  FIFO Byte Register (FBYTE) 
The FIFO Byte Register (FBYTE) indicates the effective data count in the FIFO buffer. Also, 
this register can be used to generate a receive interrupt when certain number of data sets are 
received in the receive FIFO. 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field (FBYTE2) (FBYTE1) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
The FBYTE register indicates the effective data co unt of data written from or received in FIFO. The 
following shows the settings of the FCR1:FSEL bit. 
Table 7-4 Display of data count 
FSEL FIFO selection Data count display 
0  FIFO2: Receive FIFO, FIFO1: Tran smit FIFOFIFO2=FBYTE2, FIFO1=FBYTE1 
1 FIFO2:Transmit FIFO, FIFO1:Receive  FIFO FIFO2=FBYTE2, FIFO1=FBYTE1 
 
  The initial value of data transfer coun t is 0x08 for the FBYTE register. 
   Set a data count to flag a receive  interrupt for the FBYTE register of  receive FIFO. If this specified 
transfer count matches the FBYTE register display,  the interrupt flag (SSR:RDRF) is set to 1. 
   If both conditions below are satisfied  and if the receive idle state continues for more than 8 baud rate 
clocks, the interrupt flag (RDRF) is set to 1. 
  The receive FIFO idle detection enable bit (FRIIE) is 1. 
   The number of data sets stored in the recei ve FIFO does not reach the transfer count. 
If the RDR data is read during counting of 8 clocks, this counter is reset to 0, and counting for 8 
clocks is restarted. If receive FIFO is disabled, this counter is reset to zero (0).  If data remains in the 
receive FIFO and if receive FIFO is en abled, the data counting is restarted. 
FBYTE2, FBYTE1: FIFO2 data count display bit, FIFO1 data count display bit  During writing Sets the transfer data count. 
During reading Reads the effective count of data. 
 
Read (Effective data count) 
During transmission: The number of data sets alread y written in the FIFO buffer but not transmitted yet 
During reception: The number of  data sets received in FIFO 
Write (Transfer data count)  During transmission: Set 0x00. 
During reception: Set the data count  to generate a receive interrupt. 
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7. UART (Async Serial Interface) Registers 
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FUJITSU SEMICONDUCTOR CONFIDENTIAL  56 
 
   Set 0x00 in the FBYTE register of transmit FIFO. 
   Set a data value equal to or greater than  2 in the FBYTE register of receive FIFO. 
   This state can be changed only after the data reception has been disabled. 
   A read-modify-write instruction cannot be used for this register. 
   Any setting exceeding the FIFO  capacity is inhibited. 
   When all the following requirements  are met, the receive data full flag bit (SSR:RDRF) is not set to 1 
even though the effective data of  FBYTE setting number exist in the r eceive FIFO. If the FBYTE register 
is set to 2 or greater, this operation will not occur. 
  FBYTE is set to 1. 
   The effective data count is 1, same as  the number specified in FBYTE register. 
   When the multi function serial interface macro r eceives the data, and writes received data in the 
reception FIFO, the data of the receptio n FIFO are read at the same time.   
However, after that, the receive data full flag bit (S SR:RDRF) will be set to 1 at any of the following 
conditions. 
  The next data is received. 
   The receive idele state of 8 bits  or longer is detected when the receive FIFO idele is enabled 
(FCR:FRIIE=1)  
 
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1. Outline of CSIO (Clock Sync Serial Interface) 
 
Chapter: CSIO (Clock Sync Serial Interface) 
This chapter explains the Clock Sync Serial Interface (CSIO) function that is supported in 
Operation mode 2. This CSIO is a part of the multifunction serial interface functions. 
 
1.
 Outline of CSIO (Clock Sync Serial Interface) 
2. CSIO (Clock Sync Serial Interface) interrupts 
3. CSIO (Clock Sync Serial Interface) operations 
4. Dedicated baud rate generator 
5. CSIO (Clock Sync Serial Interface) registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FM15C-E05.2 
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CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
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1. Outline of CSIO (Clock Sync Serial Interface) 
 
1.  Outline of CSIO (Clock Sync Serial Interface) 
The CSIO is a generic serial data communication interface (supporting the SPI) to allow 
synchronous communication with an external device. It also has transmit/receive FIFO (up to 
128 × 9 bits each) *1installed. 
  CSIO (Clock Sync Serial  Interface) functions 
 
   Function 
1 Data buffer 
  Full duplex double buffer (when FIFO is not used) 
   Transmit/Receive FIFO (up to 128 × 9 bits each) *1 (if FIFO is 
used) 
2 Transfer system  
  Clock synchronization (without start/stop bit) 
   Master/slave function 
   SPI supported (for both master and slave modes) 
3 Baud  rate 
  Dedicate baud rate generator provided (configured with a 15-bit 
reload counter; in master mode operation) 
   An external clock can be entere d (in the slave mode operation). 
4 Data length  Variable from 5 bits to 9 bits 
5 Receive error det ection Overrun error 
6 Interrupt request  
  Receive interrupt (a receive completion, an overrun error) 
   Transmit interrupt (a transmit data empty, a transmit bus idle) 
   Transmit FIFO interrupt (when transmit FIFO is empty) 
   Extended intelligent I/O service (EIIOS) and DMA transport 
support functions provided for  both transmission and reception 
7 Sync mode  Master or slave function 
8 Pin access  The serial data output pin can be set to 1. 
9 FIFO options 
  FIFO for transmit/receive insta lled (maximum capacity: 128 × 9 
bits for transmit FIFO, 128  × 9 bits for receive FIFO) 
*1  
   Transmit FIFO or receive FIFO can be selected. 
   Transmit data can be resent. 
   Receive FIFO interrupt timing  can be changed via software. 
   FIFO resetting is supported independently. 
*1 The FIFO capacity depends on the package type. 
 
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