Fujitsu Series 3 Manual

							FUJITSU SEMICONDUCTOR LIMITED 
5.16.  Interrupt Clear Register (INT_CLR) 
The INT_CLR clears interrupt causes. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  FCSC Reserved PCSC  SCSC MCSC 
Initial value     1b0    1b0 1b0 1b0 
Attribute     W    W W W 
 Register functions 
[bit 7:6] RES: Reserved bits 
0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 5] FCSC: Anomalous frequency detection interrupt cause clear bit 
Bit Description 
When 0 is  written  The FCS interrupt cause is not affected by the written value. 
When 1 is 
written  Clears the FCS interrupt cause. 
When read 
The fixed value 0 is read. 
 
[bit 4:3] RES: Reserved bits  0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 2] PCSC: PLL oscillation stabilizati on completion interrupt cause clear bit 
Bit Description 
When 0 is 
written  The PLL oscillation stabilization completion interrupt cause is not affected by the 
written value. 
When 1 is 
written  Clears the PLL oscillation stabilization completion interrupt cause. 
When read 
The fixed value 0 is read. 
 
[bit 1] SCSC: Sub oscillation stabilizati on completion interrupt cause clear bit   
Bit Description 
When 0 is 
written  The sub oscillation stabilization completion interrupt cause is not affected by the 
written value. 
When 1 is 
written  Clears the sub oscillation stabilization completion interrupt cause. 
When read 
The fixed value 0 is read. 
 
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[bit 0] MCSC: Main oscillation stabilization completion interrupt cause clear bit   
Bit Description 
When 0 is 
written  The main oscillation stabilization completion interrupt cause is not affected by the 
written value. 
When 1 is 
written  Clears the main oscillation stabilization completion interrupt cause. 
When read 
The fixed value 0 is read. 
 
 
When t h

is register is cleared, the interrupt status bit of the INT_STR is als o
  cleared. 
 
 
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6.  Clock Generation Unit Usage Precautions 
This section explains the precautions for using the clock generation unit. 
  The oscillation stabilization wait time of main and sub oscillators 
Because the stabilization wait time of main/sub os cillator depends on the oscillator type (crystal, 
ceramic, etc.), the wait time suitable for the oscillator type must be selected. 
   Changing the frequency division under stabilized PLL oscillation 
When the PLL frequency division ratio is changed after stabilization of PLL oscillation, stop the PLL 
oscillation once, change the frequency division ratio, and then re-enable the PLL oscillation. 
   Peripherals independent of clock control by the clock generation unit 
The following peripherals run independently of clock control by the clock generation unit. 
For information about how to handle each operating clock, see each relevant chapter. 
   USB operating clock generation unit  :  See Chapter USB Clock Generation. 
   Clock supervisor  :  See Chapter Clock supervisor. 
   Watchdog Timer  :  See Chapter Watchdog Timer. 
   Watch counter  :  See Chapter Watch Counter. 
   CAN prescaler  :  See Chapter CAN Prescaler. 
 
   Setting the oscillation stabilization wait time 
Set the oscillation stabilization wait time of the main,  sub, and PLL oscillators with relevant oscillation 
stabilization wait time setup registers, and then enable each oscillator. 
Do not change the oscillation stabilization wait time while waiting for oscillation to stabilize. 
   Checking main oscillation while using the PLL clock 
It is prohibited to stop main oscillation while using PLL oscillation. 
   Switching clock modes 
Clock modes can be switched by changing the SCM_CTL.RCS register. 
To switch clock modes, take the following steps: 
1.  Set the oscillation stabilization wait time of each oscillator. 
2.  Set the oscillation enable bit of the desired clock (SCM_CTL.xxxE) to 1. 
3.  Check the oscillation stable bit of the desired clock (SCM_CTL.xxxRDY) to 1. 
4.  Switch SCM_CTL.RCS. 
5.  Wait until SCM_STR.RCM = SCM_CTL.RCS. 
 
   Correlation between the clock mode switching and the oscillation stable bit 
The timings when the oscillation stable bit (SCM_STR.xxxRDY) turns to 1 vary for the following clock 
mode switching. 
   When switching from the high-speed CR run, main run, or main PLL run to another clock mode: 
Setting SCM_CTL.xxxE to 1 can start the oscillation stabilization wait time. You can check that 
SCM_STR. xxxRDY is 1 after the oscillation stabilization wait time has elapsed. 
   When switching from the low-speed CR run or sub run to the high-speed CR run, main run, or PLL run: 
Setting SCM_CTL.MOSCE (or .PLLE) to 1 does not start the oscillation stabilization wait time. To 
start the main (or high-speed CR or PLL) oscillation stabilization wait time, SCM_CTL.RCS must 
be switched. After the oscillation stabilization wait time has elapsed, you can check that 
SCM_STR.xxRDY is 1. 
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6. Clock Generation Unit Usage Precautions 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Clock 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  38 
   If the standby mode is released by an interrupt, the device restarts in the clock mode that indicated by the 
RCM bit in the SCM_CTL. 
 
   If any reset occurs other than software resets, the hi gh-speed CR clock (CLKHC) is set as a master clock. 
In addition, high-speed CR clock mode is set as clock mode. 
 
   If any reset other than software resets is executed, the main and sub oscillators, and PLL oscillation stop. 
If you want to use those oscillators again after the reset, enable them using the SCM_CTL. 
 
   For the correlation between each clock mode and star t/stop of the oscillation, see Chapter Low Power 
Consumption Mode. 
 
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Chapter: High-Speed CR Trimming 
This chapter explains the High-Speed CR Trimming Function. 
 
1.
 High-Speed CR Trimming Function Overview 
2. High-Speed CR Trimming Function Configuration and Block Diagram 
3. High-Speed CR Trimming Function Operation 
4. High-Speed CR Trimming Function Setup Procedure Example 
5. High-Speed CR Trimming Function Register List 
6. High-Speed CR Trimming Function Usage Precautions 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFCRTRIM-E01.0 
CHAPTER  2-2: High-Speed  CR Trimming 
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1.  High-Speed CR Trimming Function Overview 
This section explains frequency trimming function of the internal high-speed CR oscillator. 
The internal high-speed CR oscillators used for this device have fluctuation in frequency accuracy due to 
process variation. The fluctuation range of frequency accuracy can be reduced by configuring the trimming 
function. 
The frequency trimming setup has the following functions: 
   It can be configured the high-speed CR frequency trimming by writing a trimming value to the 
Frequency Trimming Register (MCR_FTRM). 
   It can be calculated the value set to the Frequency Trimming Register from the count value within a 
certain period by using input capture. 
 
For the high-speed CR frequency accuracy, see elect ric characteristics described in Data Sheet. 
 
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2.  High-Speed CR Trimming Function Configuration and Block Diagram 
This section explains the configuration and bloc k diagram of internal high-speed CR oscillator 
frequency trimming function. 
Figure 2-1 shows the block diagram of internal high-speed CR frequency trimming function. 
Figure 2-1 Block diagram of the High-speed CR Oscillator Timing Circuit 
 
CLKHC_divCLKHC
TRD
APB 
signal
APB
Interface
Multi Function Timer
Input Capture
High-speed CR OSC macro
High-speed CR  frequency 
trimming
Control circuit  register
 
 
 Configuration 
  High-speed CR macro 
A macro of the high-speed CR clock outputs CLKHC (high-speed CR clock). 
  High-speed CR Trimming Control Circuit and registers 
A control circuit and registers for trimming high-speed CR. 
  Multi-function timer input capture 
This block counts frequency before setting to calcu late the frequency trimming data for high-speed CR. 
 
For th e clo

ck definition, see Chapter Clock. 
  
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3.  High-Speed CR Trimming Function Operation 
This section explains operation conducted by frequency trimming function of the internal 
high-speed CR oscillator. 
 Operation of high-speed CR oscilla tion frequency trimming function 
  Frequency trimming setup 
  The setup process writes a trimming data value to the Frequency Trimming Register (MCR_FTRM) to 
correct the misalignment of CR frequency  accuracy caused by process variation. 
 Register lock function 
Write protect function is provided for the Frequency Trimming Register (MCR_FTRM), 
a function that protects the register from being rewritten without authorization when the system runs out of 
control. 
  Trimming data acquisition 
Data written to the Frequency Trimming Register (M CR_FTRM) can be acquired by one of the following 
three methods: 
   Use the factory preset value stored in th e CR trimming area inside flash memory. 
   Calculate by yourself the value set to the Frequency Trimming Register from the count value within a 
certain period by using input capture. 
   Output CR oscillation to an external pin, monitor the waveform to trim the frequency. 
 
 
  Erasing flash  me

mory also erases the CR trimming  area inside the me
 mory at the same time. If you use 
a value in the CR trimming area, th erefore, save the data to other area (such as RAM) before erasing 
the flash memory, 
or only erase sectors other th an in the CR trimming area. 
   For the address of the CR trimming  area, see Flash Programming Manual. 
 
 
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4.  High-Speed CR Trimming Function Setup Procedure Example 
This section provides an example of setting up frequency trimming function of the high-speed 
CR oscillator. 
 Frequency trimming setup 
Take the steps shown in the following  Figure 4-1 to set up frequency trimming. 
Figure 4-1 Frequency trimming setup 
 
End 
Lock the register 
MCR_RLR.TRMLCK = 0x000_0000 
Register settings 
MCR_FTRM.TRD 
Unlock the register 
MCR_RLR.TRMLCK = 0x1ACC_E554
  
Sta r t 
* Write other than 0x1ACC_E554 
1.  Write 0x1ACCE554 to the TRMLCK[31:0] Register to unlock the MCR_FTRM Register. 
2.  Set the MCR_FTRM. 
3.  Write a  v

alue other than 0x1ACCE554 to the TRMLCK[31:0] Register to lock the MCR_FTRM 
Register. 
  Frequency trimming da ta acquisition example 
When acquiring the data from the CR trimming area in flash memory, 
Read the CR trimming area in flash memory and get the data. 
Write the acquired value to the Frequency Trimming Register (MCR_FTRM). 
 
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 How to calculate the frequency trimming data 
The following explains how to calculate the trimming data of high-speed CR oscillation. 
1.  Let Ytgt, a target oscillation frequency be 4M[Hz]. Let Xtrm be the TRD value at the time. 
2.  Let Xtrmmin be the initial value of the TRD bit - 20% value. Let Ymin[Hz] be the frequency at this 
time. 
3.  Let Xtrmmax be the initial value of the TRD bit + 20% value. Let Ymax[Hz] be the frequency at this 
time. 
4.  The following expressions give TRD set value Xtrm , amounting to target oscillation frequency Ytgt. 
 
(Tilt)   K=Ymax - Ymin
Xtrmmax - Xtrmmin 
Xtrm
(TRD set value)   =Ytgt - Ymin
K
+ Xtrmmin 
 
Example: When Ytgt = 4MHz, Ymax=4.8MHz, Ymin=3.2MHz, Xtrmmax=d130 and Xtrmmin=d100, the  value Xtrm becomes as follows: 
   K = 4.8 M - 3.2M130 - 100
= 53333 
Xtrm =4M -  3.2M53333
+ 100 = 115 
Figure 4-2 Method to trim high-speed CR oscillation 
TRD
F[ Hz]
Ymax
Ymin
Ytgt
Xtrm
Xtrmmax
Xtrmmin 
 
 
For informatio n a

bout how to measure Ymin and Ymax, see  Example trimming data acquisition using 
input captu re. 
 
 
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