Fujitsu Series 3 Manual

							 
5. USB Function Registers 
 
5.7.  EP0I Status Register (EP0IS) 
The EP0I Status Register (EP0IS) indicates the status of the Endpoint 0 transfer in the IN 
direction. 
The following figure shows the bit configuration of the EP0I Status Register (EP0IS). bit 15 14 13 12 11 10 9 8 
Field BFINI DRQIIE - - - DRQI - - 
Attribute  R/W R/W -  - - R/W  - - 
Initial value  1 0 X  X X 1 X  X 
BFINI reset  1 Irrelevant  X X X 1 X  X 
  bit  7 6 5  4 3 2 1 0 
Field  - - -  - - - - - 
Attribute - - -  - - - - - 
Initial value X X X  X X X X X 
BFINI reset  X X X  X X X X X 
 
The following explains the function of each bit in the EP0I Status Register (EP0IS). 
[bit 15] BFINI: Send Buffer In itialization Bit (BuFfer INItial) 
This bit initializes the send buffer of transfer data. In addition, this bit is automatically set to 1 when the 
RST bit in the UDC Control Register (UDCC) is set to 1. If the RST bit was used for resetting, therefore, 
set the RST bit to 0 before clearing this bit. 
Bit Description 
0  Clears the initialization 
1 Initializes the send buffer 
 
 
Initializatio n

 by the BFINI bit initializes the buffer and  the DRQI bit. Before in
 itializing the buffer, make 
sure that the DRQI or DRQO bit is set, and there is  no access from the host, and then configure the STAL 
bit if necessary. 
 
[bit 14] DRQIIE: Send Data Interrupt Enable Bit (Data ReQuest In Interrupt Enable)  This bit enab les 

interrupts generated by the DRQI interrupt cause of the EP0I Status Register. 
Bit Description 
0 Disables interrupts generated by the DRQI cause. 
1 Enables interrupts generated by the DRQI cause. 
 
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[bit 13:11] Undefined bits The written value has no effect. The read value is undefined. 
 
[bit 10] DRQI: Send/Receive Data Interrupt Request Bit (Data ReQuest In)  This bit indicates that the IN packet transfer from the EP0 host normally ended and data was read out from 
the send buffer, so that the next send data can be wr itten.The DRQI bit is an interrupt cause, and writing 1 
is ignored.Clear it by writing 0.A read-modify-write access reads the bit as 1. 
Bit Description 
0  Clears the interrupt cause 
1  Send data can be written to the send buffer 
 
 
This  b

it must be cleared after data has been written to th e send buffer.Also
  while this bit is not set, 0 must 
not be written. 
Data can be written to the send buffer when DRQI is  1.Also when the DRQI bit is cleared, data has been 
set to the send buffer.When an IN packet request is  received while the DRQI bit is 1, therefore, NAK is 
sent automatically to the host. 
 
[bit 9:0] Undefined bits  The written val u

e has no effect. The read value is undefined. 
 
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5.8.  EP0O Status Register (EP0OS) 
The EP0O Status Register (EP0OS) indicates the status of the Endpoint 0 transfer in the OUT 
direction. 
The following figure shows the bit configuration of the EP0O Status Register (EP0OS). bit 15 14 13 12 11 10 9 8 
Field BFINI DRQOIE SPKIE - - DRQO SPK Reserved
Attribute  R/W R/W R/W  - - R/W  R/W  - 
Initial value  1 0 0  X X  0 0 0 
BFINI reset  1 Irrelevant  Irrelevant X X  0 0 0 
  bit  7 6 5  4 3 2 1 0 
Field Reserved SIZE 
Attribute - R R  R R R  R R 
Initial value X X X  X X X X X 
BFINI reset  X X X  X X X X X 
 
The following explains the function of each bit in the EP0O Status Register (EP0OS). 
[bit 15] BFINI: Receive Buffer Initialization Bit (BuFfer INItial)  This bit initializes the receive buffer  for transfer data.This bit is also automatically set by setting the RST bit 
of the UDC Control Register (UDCC). If the RST bit wa s used for resetting, therefore, set the RST bit to 
0 before clearing this bit. 
Bit Description 
0  Clears the initialization 
1 Initializes the receive buffer 
 
 
Initializatio n

 by the BFINI bit initializes the DRQO and SPK bits. Before initializing the buffer, make sure 
that the DRQI or DRQO bit is set, a n

d there is no access from the host, and then configure the STAL bit if 
necessary. 
 
[bit 14] DRQOIE: Receive Data Interrupt Enable Bit (Data ReQuest Out Interrupt Enable)  This bit enab les 

interrupts generated by the DRQO interrupt cause of the EP0O Status Register. 
Bit Description 
0 Disables interrupts generated by the DRQO cause 
1 Enables interrupts generated by the DRQO cause 
 
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[bit 13] SPKIE: Short Packet Interrupt Enable Bit (SPK Interrupt Enable) 
This bit enables interrupts generated by the SPK  interrupt cause of the EP0O Status Register. 
Bit Description 
0 Disables interrupts generated by the SPK cause 
1 Enables interrupts generated by the SPK cause 
 
[bit 12:11] Undefined bits  The written value has no effect. The read value is undefined. 
  [bit 10] DRQO: Receive Data Interr upt Request Bit (Data ReQuest Out) 
This bit indicates that the OUT packet transfer from  the EP0 host normally ended, and data has been written 
to the receive buffer, which can be read out.This bit is an interrupt caus e, and writing 1 is ignored.Clear it 
by writing 0. A read-modify-wr ite access reads the bit as 1. 
Bit Description 
0 Clears the interrupt cause 
1 Received data can be read from the receive buffer 
 
 
This bit m u

st be cleared after data has been read from  the receive buffer.
 Also while this bit is not set, 0 
must not be written. 
The receive buffer is not updated when DRQO is 1. The update is allowed when DRQO is cleared. When 
an OUT packet request is received wh ile the DRQO bit is 1, therefore, NAK is sent automatically to the 
host. 
 
[bit 9] SPK: Short Packet Interrupt Request Bit (Short PacKet)  This bit ind i

cates that the data si ze transferred from the host does  not satisfy the maximum packet size 
(including 0-byte) set by PKS in the EP0 Control Register (EP0C) when the data has been received 
successfully. This bit is an interrupt cause, an d writing 1 is ignored.Clear it by writing 0. A 
read-modify-write access r eads the bit as 1. 
Bit Description 
0 Received data size satisfies the maximum packet size 
1 Received data size does not satisfy the maximum packet size 
 
[bit 8:7] Reserved bits  These bits are reserved. The written value has  no effect. They are always read as 0. 
  [bit 6:0] SIZE: Packet Size Indication Bit (packet SIZE)  This bit indicates the number of data bytes written to the receive buffer after EP0s OUT packet transfer has 
finished. The SIZE bit is updated to a valid value wh en the DRQO interrupt cause of the EP0O Status 
Register (EP0OS) has been set. 
Example: 8 bytes => 0x08, 64 bytes => 0x40 (maximum value) 
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5.9.  EP1 to 5 Status Registers (EP1S to EP5S) 
The EP1 to 5 Status Registers (EP1S to EP5S) indicate the status of the Endpoints 1 to 5. 
The following figure shows the bit configuration of the EP1 to 5 Status Registers (EP1S to EP5S). 
 EP1 Status Register (EP1S) 
bit  15 14 13  12 11 10  9 8 
Field BFINI  DRQIE SPKIE Reserved BUSY DRQ  SPK SIZE1 
Attribute  R/W R/W R/W  - R R/W  R/W  R 
Initial value  1 0 0  X 0 0  0 X 
  bit  7 6 5  4 3 2 1 0 
Field SIZE1 
Attribute  R R R  R R R R R 
Initial value X X X  X X X X X 
 
  EP2 to 5 Status Registers (EP2S to EP5S) 
bit  15 14 13  12 11 10  9 8 
Field BFINI  DRQIE SPKIE Reserved BUSY DRQ  SPK Reserved
Attribute  R/W R/W R/W  - R R/W  R/W  - 
Initial value  1 0 0  X 0 0  0 X 
  bit  7 6 5  4 3 2 1 0 
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Field  Reserved SIZE

2 to SIZE5 
Attribute - R R  R R R  R R 
Initial value 0 X X  X X X  X X 
 
The following explains the function of each bit in  the EP1 to 5 Control Registers (EP1S to EP5S). 
[bit 15] BFINI: Send/Receive Buffer  Initialization Bit (BuFfer INItial) 
This bit initializes the send/receive buffer of transfer  data. The BFINI bit is also automatically set by setting 
the RST bit of the UDC Control Register (UDCC). If th e RST bit was used for resetting, therefore, set the 
RST bit to 0 before clearing the BFINI bit. 
Bit Description 
0  Clears the initialization 
1 Initializes the send/receive buffer 
 
 
The EP 1 to 

EP5 send/receive buffer has a double-bu ffer configuration, T
 he BFINI bit initialization 
initializes the double buffers concurrently and also  initializes the DRQ and SPK bits. Before initializing the 
buffer, make sure that the DRQ bit is set, and check th e BUSY bit to make sure that there is no access from 
the host, and then configure the STAL bit. 
 
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[bit 14] DRQIE: Packet Transfer Interrupt Enable Bit (Data ReQuest Interrupt Enable) This bit enables interrupts generated by the DRQ  interrupt cause of the EP1 to EP5 Status Register. 
Bit Description 
0 Disables interrupts generated by the DRQ cause 
1 Enables interrupts generated by the DRQ cause 
 
 
To 

use the automatic buffer transfer mode (DMAE = 1) , set DMA and enables transfer before en
 abling the 
DRQIE bit. 
 
[bit 13] SPKIE: Short Packet Interr upt Enable Bit (SPK Interrupt Enable) 
This bit en ab

les interrupts generated by the SPK  interrupt cause of the EP1 to EP5 Status Register. 
Bit Description 
0 Disables interrupts generated by the SPK cause 
1 Enables interrupts generated by the SPK cause 
 
[bit 12] Reserved bit  This bit is reserved. The written value has no effect. The read value is undefined. 
 
[bit 11] BUSY: Busy Flag Bit (BUSY flag)  This bit indicates that the host is  currently gaining write or read access to the send/receive buffer. The 
BUSY bit is automatically set or reset. 
Bit Description 
0  No access from the host 
1  Write or read access from the host is in process 
 
 
If the B

USY bit is set while the DRQ bit is set, it indicat es that the host is currently accessing either 
 of the 
double buffers that is not acce ssed by the CPU or via DMA. 
Usually, control using the BUSY bit is not required. To  initialize the buffer by setting BFINI, however, take 
the following steps previously. 
1.  Make sure that the DRQ bit has been set, and check  the BUSY bit to make sure that there is no access 
from the host. 
2.  Set the STAL bit. 
 
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[bit 10] DRQ: Packet Transfer Interrupt Request Bit (Data ReQuest) This bit indicates that the EP1 to EP5 packet transfer has normally ended, and processing of the data is 
required.The DRQ bit is an interrupt cause, and wr iting 1 is ignored.Clear the DRQ bit by writing 0 
while it is 1. A read-modify-wr ite access reads the bit as 1. 
Bit Description 
0 Clears the interrupt cause 
1  Packet transfer normally ended 
 
 
If auto m

atic buffer transfer mode (DMAE = 1) is not  u
 sed, 0 must be written to the DRQ bit after data has 
been written or read to/from the se nd/receive buffer.Switch the access buffers once the DRQ bit is cleared. 
That DRQ = 0 may not be read after the DRQ bit is cl eared.If the transfer direction is set to IN, and the 
DRQ bit is cleared without writing buffer data while the DRQ bit is 1, it implies that 0-byte data is set.If 
DIR of the EP1 to EP5 Control Registers (EP1C to EP5C) is set to 1 at initial settings, the DRQ bit of 
corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, 0 must not be written. 
 
[bit 9] SPK: Short Packet Interrupt Request Bit (Short PacKet)  This bit ind i

cates that the data si ze transferred from the host does  not satisfy the maximum packet size 
(including 0-byte) set by PKS in the EP1 to EP5 Control Registers (EP1C to EP5C) when the data has been 
received successfully. This bit is an  interrupt cause, and writing 1 is ignored.Clear it by writing 0.A 
read-modify-write access r eads the bit as 1. 
Bit Description 
0 Received data size satisfies the maximum packet size 
1 Received data size does not satisfy the maximum packet size 
 
 
The SPK 

bit is not set during data transfer in the IN direction. 
 [EP2 to EP5: bit 8:7] Reserved bits  In EP2 to EP5, these  b

its are reserved.The written va lue has no effect. They are always read as 0. 
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[(EP1: bit 8:7) bit 6:0] SIZE: packet SIZE These bits indicate the number of data bytes written to the receive buffer when OUT packet transfer of EP1 
to EP5 has finished. The SIZE bit is updated to a valid value when the DRQ interrupt cause of the EP1 to 
EP5 Status Registers (EP1S to EP5S) has been set. 
The maximum transfer data size of Endpoints 1 to 5 is as follows: 
EndPoint  Maximum transfer size  Indication range 
1 256 bytes  0x000 to 0x100 
2 to 5 64 bytes  0x00 to 0x40 
 
 
These  b

its are set to the data size transferred from th e host in the OUT d
 irection and written to the buffer. 
Therefore, a value read during transfer  in the IN direction has no effect. 
 
 
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5.10.  EP0 to 5 Data Registers (EP0DTH to EP5DTH/EP0DTL to EP5DTL) 
The EP0 to 5 Data Registers (EP0DTH to EP5DTH/EP0DTL to EP5DTL) control writing or 
reading transfer data to/from the send/receive buffer for Endpoints 0 to 5. 
The following figure shows the bit configurati on of the EP0 to 5 Data Registers (EP0DTH to 
EP5DTH/EP0DTL to EP5DTL). 
  EP0DTH to EP5DTH 
bit  15 14 13  12 11 10  9 8 
Field BFDT 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value X X X  X X X X X 
 
  EP0DTL to RP5DTL 
bit  7 6 5  4 3 2 1 0 
Field BFDT 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value X X X  X X X X X 
 
The following explains the function of each bit  in the EP0 to 5 Data Registers (EP0DTH to 
EP5DTH/EP0DTL to EP5DTL). 
[bit 15:0] BFDT: Endpoint Send/Receive Buffer Data Bits (BuFfer DaTa)  A register used for data write/read to/from  the send/received buffer for each end point. 
 
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Chapter: USB Function 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  63 
    The CPU can access the EP0 to 
 5 Data Registers (EP0DTH    to EP5DTH/EP0DTL to EP5DTL) either 
by the byte or by the half-word. 
   Byte access 
First access low-order (EPxDTL) and then high-o rder (EPxDTH). Subsequently, access low-order 
(EPxDTL) and high-order (EPxDTH) alternately. 
   This register must not be accessed  by the bit operation instruction. 
 
Example: Setup transfer  by the Get descriptor
Incoming data on USB bus
Read sequence
MCU EP0DTH EP0DTL
Incoming data on USB bus
Read sequence
bit15 bit0
bit15 bit0
Example: IN transfer by the Get descriptor
MCUEP0DTH EP0DTL
Write sequence
bit15 bit0
bit15 bit0EP0DTH/EP0DTL
EP0DTH/EP0DTL
EP0DTH/EP0DTL
EP0DTH/EP0DTL
EP0DTL
EP0DTH
EP0DTL
EP0DTH
EP0DT
EP0DTL
EP0DTH EP0DTL
EP0DTH
EP0DTL
EP0DTH
EP0DTL
EP0DT EP0DTH
EP0DTL
EP0DTH EP0DTL
EP0DTH EP0DTL
            EP0DTL
EP0DTH/EP0DTL
EP0DTH/EP0DTL
EP0DTH/EP0DTL
EP0DTH/EP0DTL
Byte read by 
CPU
Half-word read  by CPU
Byte write by CPU
Half-word write  by CPU
Outgoing data on USB bus
Outgoing data on USB bus Write sequence
+1 +0
+1 +0
00
H(8th byte)
09H(7th byte)00H(6th byte) 00H(5th byte)02H(4th byte) 00H(3rd byte)06H(2nd byte) 80H(1st byte)
00
H(8th byte) 09H(7th byte)
00
H(6th byte)
00H(5th byte)
02
H(4th byte)
00H(3rd byte)
06
H(2nd byte)
80H(1st byte)
00
H(8th byte)09
H(7th byte)
00
H(6th byte)
00
H(5th byte)02
H(4th byte)
00
H(3rd byte)
06
H(2nd byte) 80
H(1st byte)
00
H(8th byte) 09H(7th byte)
00
H(6th byte)
00H(5th byte)
02
H(4th byte)
00H(3rd byte)
06
H(2nd byte)
80H(1st byte)
E0
H(8th byte) 00H(7th byte)
01
H(6th byte)
01H(5th byte)
00
H(4th byte)
10H(3rd byte)
02
H(2nd byte)
09H(1st byte)
32
H(9th byte)
09
H(1st byte)
02H(2nd byte) 10H(3rd byte) 00H(4th byte)01H(5th byte) 01H(6th byte)00H(7th byte)) E0H(8th byte)32H(9th byte)
E0
H(8th byte)00
H(7th byte)01
H(6th byte)
01
H(5th byte)00
H(4th byte)
10
H(3rd byte) 02
H(2nd byte) 09
H(1st byte)
32
H(9th byte)E0
H(8th byte) 00H(7th byte)
01
H(6th byte)
01H(5th byte)
00
H(4th byte)
10H(3rd byte)
02
H(2nd byte)
09H(1st byte)
32
H(9th byte)
 
The DMA transfer can only access the EP0 to 5  Data Registers (EP0DTH to EP5DTH/EP0DTL to 
EP5DTL) by the half-word. (See  Automatic data size transfer mode of 3.6 DMA transfer function ) 
 
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