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9. Descriptions of base timer functions 
 
 Timer Control Register (L ow-order bytes of TMCR) 
 
bit 7 6 5 4 3 2 1 0 
Field res FMD2 FMD1 FMD0 OSEL  MDSE CTEN STRG 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 6:4] FMD2 to FMD0: Timer function selection bits    These bits select the timer function. 
   When the FMD2, FMD1, and FMD0 bits are set to 0b010, the PPG function is selected. 
   Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make 
changes at the same time you set 1 to the CTEN bit. 
Bit 6  Bit 5Bit 4  Description 
0 0 0  Reset mode 
0 0 1  Selection of the PWM function 
0 1 0  Selection of the PPG function 
0 1 1  Selection of the reload timer function 
1 0 0  Selection of the PWC function 
1 0 1 
1 1 0 
1 1 1  Setting disabled 
 
[bit 3] OSEL: Output polarity specification bit    This bit sets the polarity of the PPG output. 
Polarity After reset  Completion of LOW 
width counting  Completion of HIGH 
width counting 
Normal LOW output   
  
 
Inverted HIGH output 
 
  
 
 
Bit Description 
0 Normal 
polarity 
1 Inverted  polarity 
 
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[bit 2] MDSE: Mode selection bit   This bit selects continuous pulse output or one-shot pulse output. 
   Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make 
changes at the same time you set 1 to the CTEN bit. 
Bit Description 
0 Continuous  operation 
1 One-shot operation 
 
[bit 1] CTEN: Count operation enable bit    This bit enables the operation of the down counter. 
   When the counter is in operation en abled status (the CTEN bit is 1), writing 0 to this bit stops the 
counter. 
Bit Description 
0 Stop 
1 Operation  enabled 
 
[bit 0] STRG: Software trigger bit    When the CTEN bit is 1, writing 1 to the STRG bit enables software triggering. 
   The read value of the STRG bit is always 0. 
 
  Soft ware triggering

 is also enabled when 1 is  written to the CTEN and
  STRG bits simultaneously. 
   If the STRG bit is set to 1, software triggering  is enabled regardless of the EGS1 and EGS0 settings. 
 
Bit Description 
0 Invalid 
1 Start triggered by software 
 
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 Timer Control Register 2 (High-order bytes of TMCR2) 
 
bit 15 14 13 12 11 10 9 8 
Field res CKS3 
Attribute R/W  R/W 
Initial value 0b0000000  0 
Note:  This register is placed above the STC register. 
[bit 15:9] res: Reserved bits  The read value is 0. 
Set 0 to this bit. 
 
[bit 8] CKS3: Count clock selection bit  See Count clock selection bit in  9.2.6 Timer Control Register (High-order bytes of TMCR). 
 
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 Status Control Register (STC) 
 
bit 7 6 5 4 3 2 1 0 
Field res TGIE res UDIE res TGIR res UDIR 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
Note:  The TMCR2 register is placed in the upper bytes of this register. 
[bit 7] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 6] TGIE: Trigger interrupt request enable bit    This bit controls interrupt requests of bit 2 TGIR. 
   When the TGIE bit is enabled, setting bit 2 TGIR  generates an interrupt request to the CPU. 
Bit Description 
0 Disables interrupt requests. 
1  Enables interrupt requests. 
 
[bit 5] res : Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 4] UDIE: Underflow interrupt request enable bit    This bit controls interrupt requests of bit 0 UDIR. 
   When the UDIE bit is enabled, setting bit 0 UDIR generates an interrupt request to the CPU. 
Bit Description 
0 Disables  interrupt requests. 
1  Enables interrupt requests. 
 
[bit 3] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
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[bit 2] TGIR: Trigger interrupt request bit   When a software trigger or trigger input is detected, the TGIR bit is set to 1. 
   The TGIR bit is cleared by writing 0. 
   Even if 1 is written to the TGIR  bit, the bit value is not affected. 
   The read value of read-modify-write instructions is 1 regardless of the bit value. 
Bit Description 
0  Clears an interrupt cause. 
1 Detects an interrupt cause. 
 
[bit 1] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 0] UDIR: Underflow interrupt request bit    When a count value underflow from 0x0000 to 0xFFFF occurs during counting from the value for which 
the HIGH width is set, the UDIR bit is set to 1. 
   The UDIR bit is cleared by writing 0. 
   Even if 1 is written to the UDIR bit, the bit value is not affected. 
   The read value of read-modify-write instructions is 1 regardless of the bit value. 
Bit Description 
0  Clears an interrupt cause. 
1 Detects an interrupt cause. 
 
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9.2.7. LOW Width Reload Register (PRLL) 
The LOW Width Reload Register (PRLL) is a register used to set the LOW width of PPG 
output waveforms. Transfer to the Timer Register is performed at detection of a start trigger or 
at an underflow after the completion of HIGH width counting. 
 bit 15       0 
Field PRLL [15:0] 
Attribute R/W 
Initial value  0xXXXX 
 
This register is used to set the LOW width of PPG output waveforms. Transfer to the Timer Register is 
performed at detection of a start trigger and at an underflow at the completion of HIGH width counting. 
   Access the PRLL register with 16-bit data. 
   Set the LOW width for the PRLL register after setting the PPG function using the FMD2, FMD1, and 
FMD0 bits in the TMCR register. 
 
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9.2.8. HIGH Width Reload Register (PRLH) 
The HIGH Width Reload Register (PRLH) is a buffered register used to set the HIGH width of 
PPG output waveforms. Transfer from the PRLH to the buffer register is performed at 
detection of a start trigger and at an underflow after the completion of HIGH width counting. 
Transfer from the buffer register to the Timer Register is performed at an underflow at the 
completion of LOW width counting. 
 bit 15       0 
Field PRLH [15:0] 
Attribute R/W 
Initial value  0xXXXX 
 
This register is used to set the HIGH width of PPG ou tput waveforms. Transfer from the PRLH to the buffer 
register is performed at detection of a start trigger and at an underflow at the completion of HIGH width 
counting. Transfer from the buffer  register to the Timer Register is performed at an underflow at the 
completion of LOW width counting. 
   Access the PRLH register with 16-bit data. 
   Set the HIGH width for the PRLH register after setting the PPG function using the FMD2, FMD1, and 
FMD0 bits in the TMCR register. 
 
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9.2.9. Timer  Register  (TMR) 
The Timer Register (TMR) reads the value of the 16-bit down counter. 
 bit 15       0 
Field TMR [15:0] 
Attribute R 
Initial value  0x0000 
 
The value of the 16-bit down counter is read. 
   Access the TMR register with 16-bit data. 
 
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9.3.  Reload timer function 
The function of the base timer can be set to either the 16-bit PWM timer, 16-bit PPG timer, 
16/32-bit reload timer, or 16/32-bit PWC timer using the FMD2, 1, and 0 bits in the Timer 
Control Register. This section explains the timer functions available when the reload timer is 
set. 
1. Operations of the 16-bit reload timer 
2.  Reload timer operation flowchart 
3.  Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the reload 
timer is selected 
4.  PW M Cycle Set Register (PC

SR) 
5.  Timer Register (TMR) 
 
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9.3.1. Operations of the 16-bit reload timer 
In reload timer operations, countdown is performed from the value set in the PWM Cycle Set 
Register in synchronization with the count clock. This operation continues until the count 
value reaches 0 or the cycle setting is loaded automatically to stop the countdown. 
 Count operation performed when th e internal clock is selected 
To start the count operation at the same time counting  is enabled, write 1 to both CTEN and STRG bits in 
the Timer Control Register. When the timer is started  (CTEN = 1), trigger input with the STRG bit is valid 
regardless of the operation mode. 
When the count operation is enabled and the timer is star ted with a software trigger or an external trigger, 
the value in the PWM Cycle Set Register is loaded to the counter and countdown is started. 
It takes a time of 1T (T: machine cy cle) from setting of a counter start trigger to loading of the PWM Cycle 
Set Register data to the counter. 
Figure 9-13  shows the start of the counter by a software trigger and counter operation. 
Figure 9-13 Count operation performed when the internal clock is selected 
 
1T  
STRG (Register)
Load
Count clock
Count value
CTEN (Register)
Reload value
 -1  -1  
0xXXXX
  
 
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