Fujitsu Series 3 Manual
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4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 26
4.3. DMAC Operation and Control Procedure for Hardware
(EM=0) Tr a n sfer
This section describes DMAC operation and control procedure for hard ware (EM=0) transfer.
Figure 4-5 Transitional Diagram of Hard ware (EM=0) Transfer State
Hardware(EM=0) DMA operationTransition by CPU
Transition by DMAC/Periperal
2
5,6,7
4
Disable
DE=0 or EB=0 or
DH!=0000 or PB=1 initial: SS=000
after stop:SS=code
Transfer
DE=1 EB=1
DH=0000 PB=0
SS=000
Pause
DE=1 EB=1
DH!=0000 or PB=1
SS=111
8
8
1,9,13
Reset
10
11
12
Wait
1st trigger
DE=1 EB=1
DH=0000 PB=0
SS=000
3
13
Figure 4-5 shows a transitional diagram of the states of the channel to be controlled for hardware (EM=0)
transfer. The numbers next to the transitional lines in the figure correspond to the numbers which appear in
the following control procedures. T he solid transitional lines indicate transitions of state instructed by CPU,
while the broken transitional lines indicate transitions of state due to DMAC /Peripheral operation.
Some parts of the explanation below state " See the software transfer procedure". This means that where the
same control as in the software transfer procedure applies, no special mentioning is required; therefore, such
redundant explanation has been omitted. In this example, the explanation assumes that EM=0 is set.
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4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 27 Description of Ea ch State Disable state See the software transfer procedure. Wait -1st -trigger state In this state, the channel to be controlled is enabled to perform transfer. A channel in this state waits for the first transfer request from a Peripheral to be asserted. It also changes its state upon instruction from CPU. Transfer state In this state, the channel to be controlled has received the first transfer request from the Peripheral. A channel in this state performs transfer operation as specified. Once all the transf er operation is completed, it returns to Disable state. It also changes its state upon instruction from CPU. Pause state See the software transfer procedure. Explanation of Control Procedure 1. Disable state / Preparation for transfer See Step 1 in the softwa re transfer procedure. The following restrictions apply to hardware transfer. Decide in advance on which Peripheral ’s interrupt signal to be used as the transfer request signal to DMAC using the interrupt controller block (see the section on the functional explanation). Set ST=0 and specify which Peripheral ’s transfer request to be processed at the channel that will perform the transfer, by IS at the same time. Multiple channels cannot process transfer request of the same Peripheral. In the case of Demand transfer mode, set BC=0 . This section explains the operation when EM=0 is set. 2. Disable state => Wait-1st -trigger state / Transfer enabled An instruction to enable individual -channel operation is issued from CPU. When DE=1, EB=1, DH=0000 and PB=0 are set, th e channel to be controlled moves to Wa i t-1st -trigger state. 3. Wait -1st -trigger state / Start of transfer The channel in Wa i t-1st -trigger state is waiting for the transfer request signal to be asserted from the Peripheral or for an instruction from CPU. When the first transfer request signal is asserted, it moves to Transfer state. 4. Transfer state See Step 3 in the software transfer procedure. In the case of hardware transfer, a channel in Transfer state performs transfer operation by the transfer request signa l from a Peripheral, as described in Sections 3.3 and 3.4. In each mode, match the number of transfer requests from the Peripheral with the number of transfer requests required by DMAC. Below is the explanation for the operation when the number of transfer requests goes over or below the requirement in each operation mode. Figure 4-6 shows a case of Demand transfer. In the case of Demand transfer, the number of transfer requ ests required to complete the transfer is TC+1. Unless the number of transfer requests goes over or below the requirement, CPU does not have to intervene (Example 1 in Figure 4-6). If the number of transfer requests generated from the Peripheral exceeds the DMAC ’s setting for the number of transfers, DMAC moves to Disable state after the completion of the specified number of transfers. In the Disable state, no further transfers are executed. Also, as the excessive transfer request signals are not cleared from DMAC, the asserted state continues (Example 2 in Figure 4-6). If the number of transfer requests generated from the Peripheral is smaller than DMAC ’s setting for the number of transfers, DMAC waits for the remaining number of transfer requests in Transfer state (Example 3 in Figure 4-6). CHAPTER 8: DMAC MN706-00002-1v0-E 206 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 28 It is supposed that DMAC ’s transfer processing may be too slow to catch up with the generation interval of transfer requests from Peripheral. In the case of Demand transfer, the transfer request signal remains asserted; therefore, as many as TC+1 of transfers can be performed (Example 4 in Figure 4-6). Figure 4-6 Operation of Hardware- Demand Transfer DMA status Transfer Demand transfer mode (hardware DMA operation) Transfer action Disable Example 1: (TC+1)== Transfer request from Periperal Disable TC (reload) 2 1 0 SS 000 101 (normal end) Start request from CPU normal end Wait 1st trigger Transfer request 1st Transfer request from Peripheral 2 DMA status Transfer Transfer action Disable Example 2: (TC+1) < Transfer request from Periperal Disable TC (reload) 2 1 0 SS 000 101 (normal end) Wait 1st trigger Transfer request 2 DMA status Transfer Transfer action Disable Example 3: (TC+1) > Transfer request from Periperal TC (reload) 2 1 0 SS 000 Wait 1st trigger Transfer request DMA status Transfer Transfer action Disable Example 4: DMA transfer be delayed TC (reload) 2 1 0 SS 000 Wait 1st trigger Transfer request Disable 101 (normal end) CHAPTER 8: DMAC MN706-00002-1v0-E 207 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 29 Figure 4-7 shows a case of Block transfer. In the case of Block transfer, the number of transfer requests required to complete the tra nsfer is TC+1. Unless the number of transfer requests goes over or below the requirement, CPU does not have to intervene (Example 1 in Figure 4-7). Figure 4-7 Operation of Hardware- Block Transfer DMA status Transfer Block transfer mode (hardware DMA operation) Transfer actionExample1: (TC+1)== Transfer request from Periperal TC(reload)210 SS 000101 Start request from CPUNormal end Wait Transfer request 1st Transfer request from Peripheral 2 DMA status Transfer action Example2: (TC+1) < Transfer request from Periperal TC(reload) SS Transfer request Example3: (TC+1) > Transfer request from Periperal Example4: DMA transfer be delayed Transfer 210 000101 Wait 2 Dis Dis Disable Disable DMA status Transfer action TC(reload) SS Transfer request Transfer 210 000 WaitDis DMA status Transfer action TC(reload) SS Transfer request Transfer 210 000 WaitDis If the number of transfer requests generated from the Peripheral exceeds the DMAC’s setting for the number of transfers, DMAC moves to Disable state after the completion of the specified number of transfers. In the Disable state, no further transfers are executed. Also, as the excessive transfer request signals are not cleared from DMAC, the asserted state continues, In this case, deassert the transfer request signal from CPU (Example 2 in Figure 4-7). CHAPTER 8: DMAC MN706-00002-1v0-E 208 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 30 If the number of transfer requests generated from the Peripheral is smaller than DMAC ’s setting for the number of transfers, DMAC waits for the remaining number of transfer requests in Transfer state (Example 3 in Figure 4-7). It is supposed that DMAC’s transfer processing may be too slow to catch up with the generation interval of transfer requests from Peripheral. In the case of Block transfer, if DMAC ’s transfer processing is delayed from the transfer request from the Peripheral, the rising edge of the next transfer request signal during the transfer operation is ignored. Also, the transfer request signal asserted during the transfer operation is cleared from DMAC. Then, DMAC waits for the remaining transfer requests in Transfer state (Example 4 in Figure 4-7). In the case of Burst transfer, all of the (BC+1) x (TC+1) of transfers are performed when it becomes accessible to the system bus after the first trans fer request is received. The required number of transfer requests from the Peripheral is only the first one. If the number of transfer request signals generated exceeds the requirement, it is ignored in Disable state, just like Block transfer. 5. Transfer state => Disable state / Successful completion of transfer See Step 4 in the software transfer procedure. 6. Transfer state => Disable state / Transfer error stop See Step 5 in the software transfer procedure. 7. Transfer state => Disable state / End of Peripheral stop request The channel in Transfer state suspends its transfer processing, if the transfer stop request signal is asserted from the Peripheral. It clears EB, PB and ST and moves to Disable state. It sets " 010" to SS and gives the notification of the erro r stop. If interrupts have been enabled by EI, an unsuccessful transfer completion interrupt occurs. BC, TC, DMACSA and DMACDA hold the values set during the suspension of the transfer. Attention must be paid to the SS value, which is the same as the stop request from software. 8. Transfer state, Pause state => Disable state / Forced termination of transfer See Step 6 in the software transfer procedure. 9. Disable state / Post -transfer processing See Step 7 in the software transfer procedure. Normally, in the cases of stop request from Peripherals, forced termination from software and transfer error stop, the transfer request signal remains asserted, because the number of transfers processed is smaller than the number of transfer requests from the Peripheral. Instruct from CPU the Peripheral to deassert the transfer request signal. In the case of stop request from Peripherals, the transfer request signal is masked as long as the stop request signal is asserted. Also deassert the transfer stop request signal. Even i f DMAC has successfully completed the specified number of transfers, the transfer request signal may remain asserted or may be reasserted, depending on Peripheral ’s settings. Attention must be paid to the possibility that this may affect the next transfer. 10. Transfer state, Pause state / Transfer pause See Step 8 in the software transfer procedure. 11. Pause state See Step 9 in the software transfer procedure. The channel in Pause state does not execute transfer, even if the transfer request signal from the Perip heral is asserted. It does not clear the transfer request signal either. 12. Pause state / Cancellation of transfer pause See Step 10 in the software transfer procedure. When an instruction to cancel the pause is issued while it is in Pause state, it returns to Transfer state. If the transfer request signal was asserted in the previous Pause state, the operation to follow varies as shown below, depending on the transfer mode. CHAPTER 8: DMAC MN706-00002-1v0-E 209 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 31 In the case of Demand transfer mode, the transfer request signal remains asserted from the Pause state. Therefore, the transfer is resumed when DMAC returns to Transfer state, and the transfer request signal is cleared as normal. See Figure 4-8. Figure 4-8 Operation of Demand Transfer in Pause State DMA status Transfer request Pause Transfer Demand transfer mode behavior during pause state Transfer action Transfer DMA status Transfer request Pause Transfer Transfer action Transfer Case of transfer request be asserted during pause state Case of no transfer request be asserted during pause state In the case of Block transfer mode, the transfer request signal remains asserted. Even when it returns to Transfer state, the rising edge of the transfer request signal is not detected, and the transfer is not resumed. Therefore, the transfer request is ignored during Pause state. Also, the transfer request signal is not cleared from DMAC. To resume the transfer which has been put on pause, instruct from CP U the Peripheral to deassert the transfer request signal after an instruction to cancel the pause is issued to DMAC. After that, the transfer will be resumed when the next transfer request is generated from the Peripheral. In this case, attention must be p aid to the difference between the number of transfer requests output from the Peripheral and the number of transfer requests received by DMAC. See Figure 4-9. Figure 4-9 Operation of Bloc k Transfer in Pause State DMA status Transfer request Pause Transfer Block transfer mode behavior during pause state Transfer action Transfer DMA status Transfer request Pause Transfer Transfer action Transfer Case of transfer request be asserted during pause state De-assert from CPU Case of no transfer request be asserted during pause state CHAPTER 8: DMAC MN706-00002-1v0-E 210 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 32 13. Operation in Disable state and Wait -1st -trigger state See Step 11 in the software transfer procedure. If the transfer request signal is not asserted to the channel in Disable state, the specificati ons of the transfer content can be changed freely (rewriting to registers DMACSA, DMACDA, DMACA[29:0], and DMACB ). If the transfer request signal is asserted or may be asserted to the channel in Disable state, the specifications of IS, ST and MS in the tra nsfer content cannot be changed. If an attempt is made to change these settings, DMAC may perform unexpected behaviors. To change the settings of IS, ST and MS, first clear the transfer request signal to both of the Peripherals (used before and after the change) from CPU, and then always change the settings while the transfer request signal is deasserted. See Figure 4-10. Figure 4-10 Changing IS, ST and MS Settings DMA status Transfer Peripheral1 DMA request Peripheral2 DMA request Transfer Disable IS,ST ,MS can be changed . DMA status Transfer Peripheral1 DMA request Peripheral2 DMA request Disable IS,ST ,MS should not be changed . Wait 1st trigger Wait 1st trigger Transfer Changing IS ,ST,MS The specifications of the transfer content cannot be changed to the channel in Wa i t-1st -trigger state from CPU If the transfer request signal is not asserted to the channel in Wa i t-1st -trigger state, it moves to Disable state when CPU issues an instruction to disable individual - or all- channel operation or an instruction to put individual - or all- channel operation on pause. In this case, it is considered that the enabled transfer has been cancelled. In any case, SS does not change. If the transfer request signal may possibly be asserted to the channel in Wa i t-1st -trigger state, it should be noted that DMAC has already started or completed the transfer before the attempted cancellation of the enabled transfer from CPU. In Disable state, DMAC does not start the transfer or clear the transfer request, even if the transfer request signal is asserted. If it moves to Wa i t-1st -trigger state by instruction from CPU while the tr ansfer request signal is asserted, the following operation applies (only when the settings of IS, ST and MS are not intended to be changed, as explained earlier). In the case of Demand transfer mode, DMAC immediately moves to Transfer state and starts the transfer, because the transfer request signal remains asserted. The transfer request signal is cleared from DMAC as normal. See Figure 4-11 . CHAPTER 8: DMAC MN706-00002-1v0-E 211 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 33 Figure 4-11 Operation of Demand Transfer in D isable State DMA status Transfer requestWait 1st trigger Transfer Demand transfer mode behavior during disable state Transfer action Disable DMA status Transfer request Transfer Transfer actionDisable Case of transfer request be asserted during disable state Case of no transfer request be asserted during disable state Wait 1st trigger In the case of Block transfer mode, the transfer request signal remains asserted. Even when it moves to Wa i t -1st -trigger state, the rising edge of the transfer request signal is not detected, and the transfer i s not resumed. Therefore, the transfer request is ignored during Disable state. To resume the transfer, instruct DMAC to move to Wa i t-1st -trigger sate, and then instruct from CPU the Peripheral to deassert the transfer request signal. After that, it will m ove to Transfer state and the transfer will be resumed when the next transfer request is generated from the Peripheral. In this case, attention must be paid to the difference between the number of transfer requests output from the Peripheral and the number of transfer requests received by DMAC. See Figure 4-12. Figure 4-12 Operation of Block Transfer in Disable State DMA status Transfer request Transfer Block transfer mode behavior during disable state Transfer action DMA status Transfer requestWait 1st trigger Transfer Transfer actionDisable Case of transfer request be asserted during disable state De -assert from CPU Case of no transfer request be asserted during disable state Wait 1st triggerDisable CHAPTER 8: DMAC MN706-00002-1v0-E 212 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 34 Additional Matter 1 See Additional Matter 1 in the software transfer procedure. In the case of hardware transfer, always write "0" t o ST. Additional Matter 2 See Additional Matter 2 in the software transfer procedure. Additional Matter 3 See Additional Matter 3 in the software transfer procedure. Additional Matter 4 See Additional Matter 4 in the software transfer procedure. Additional Matter 5 If the tr ansfer request signal (interrupt signal) from the Peripheral needs to be deasserted, the following method is available. Normally, the interrupt signal from the Peripheral is the interrupt factor flag masked (logic AND) by the interrupt enable flag. The interrupt signal can be deasserted by resetting either of the flags. When the interrupt enable flag is reset and then set, the rising edge occurs to the interrupt signal. Following this procedure can notify DMAC of the transfer request for Block transfer agai n. For details, check the manual for each Peripheral. CHAPTER 8: DMAC MN706-00002-1v0-E 213 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 35
4.4. DMAC Operation and Control Procedure for Hardware
(EM=1) Transfer
This section describes DMAC operation and control procedure for hardware (EM= 1) transfer.
Figure 4-13 Transitional Diagram of Hardware (EM= 1) Transfer State
Hardware (EM=1) DMA operation
2
5 ,6,7
4
Disable
DE
=0 or EB =0 or
DH !=0000 or PB=1
initial : SS=000
after stop :SS=code
Transfer
DE =1 EB=1
DH =0000 PB=0
SS=000
Pause
DE =1 EB=1
DH !=0000 or PB=1
SS=111
9 ,10
10
1 ,11 ,15
Reset
12
13
14
Wait
1 st trigger
DE =1 EB=1
DH =0000 PB=0
initial :SS=000
after stop: SS=code
3
15
Transition by CPU
Transition by DMAC/Periperal
8
Figure 4-13 shows a transitional diagram of the states of the channel to be controlled for hardware (EM=0)
transfer. The numbers next to the transitional lines in the figure correspond to the numbers which appear in
the following control procedures. The solid t ransitional lines indicate transitions of state instructed by CPU,
while the broken transitional lines indicate transitions of state due to DMAC/Peripheral operation.
EM (Enable bit clear mask ) is a bit that masks EB clear upon the completion of transfer of the channel to be
controlled. EM=1 enables the same transfer process to be repeated without giving instructio ns from CPU.
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