Fujitsu Series 3 Manual

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-12 Master mode interrupt 1 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=0) 
 
  
Slave Address S WACK DataACKDataACKDataACK P or Sr
 
  




S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is written in the TDR register, and the INT bit is set to 0. 
 An interrupt occurs when a single byte is sent and an ACK is received. - The send data is written in the TDR register, and the INT bit is set to 0. 
 An interrupt occurs when a single byte is sent and an ACK is received. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT) is set, the TDRE bit is set to 1.   
 
Figure 2-13 Master mode transmit interrupt 2 by disabling FIFO    (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0, ACK response) 
 
 
 
Slave Address S WACK DataACKDataACKDataACK P or Sr
 
 


  
 

S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received. 
- The send data is written in the TDR register, and the INT bit is set to 0. 
 An interrupt occurs when a single byte is sent. - An interrupt occurs when a single byte is sent. 
 An interrupt occurs when a single byte is sent. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT) is set, the TDRE bit is set to 1. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
985 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-14 Master mode transmit interrupt 3 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0, NACK response) 
 
  
Slave Address S WACK DataACKDataACKDataNACKP or Sr
 
 



 
 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is written in the TDR register, and the INT bit is set to 0. 
 An interrupt occurs when a single byte is sent. - The send data is written in the TDR register, and the INT bit is set to 0. 
 An interrupt occurs when a single byte is sent. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT) is set, the TDRE bit is set to 1. 
 
Figure 2-15 Master mode transmit interrupt 4 by disabling FIFO (SSR:DMA=0,  IBCR:WSEL=1, IBSR:RSA=0, NACK response during transmission) 
 
  
 


 
P or SrNACKDataACK
DataACK
DataACK W
S Slave Address 
  
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received. 
- An interrupt occurs when the slave address is s ent, the direction bit is sent, and an ACK is received. 
 An interrupt occurs when a single byte is sent. 
- The send data is written in the TDR register, and the INT bit is set to 0. 
 An interrupt occurs when a NACK is responded. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT) is set, the TDRE bit is set to 1. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
986 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-16 Master mode transmit interrupt 5 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=1 -> 0, IBSR:RSA=0, ACK response) 
 
 
 
Slave Address S WACK DataACKDataACKDataACK P or Sr
 
  




S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is written in the send buffer, and the INT bit is set to 0. 
 An interrupt occurs when a single byte is sent. - The send data is written in the send buffer, and both WSEL and INT bits are set to 0. 
 An interrupt occurs when a single byte is sent. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT) is set, the TDRE bit is set to 1. 
 
Figure 2-17 Master mode interrupt 6 by disabling FIFO    (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=1) 
 
  




P or SrACK DataACK
DataACK
DataACK W
S Slave Address 
 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address (reserved address) is sent, a direction bit is sent,   
and an ACK is received. - The send data is written in the TDR register, and the INT bit is set to 0. 
 An interrupt occurs when a single byte is sent and an ACK is received.    - The send data is written in the TDR register, and the INT bit is set to 0. 
 An interrupt occurs when a single byte is sent and an ACK is received. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT) is set, the TDRE bit is set to 1. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
987 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-18 Master mode transmit interrupt 7 by enabling FIFO   (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=0, ACK response) 
 
 
 
 
  
P or SrACK Data ACK
DataACK
DataACK W
S Slave Address 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if the Send FIFO buffer is emptied.   
- The send data is written in the Send FIFO buffer, and INT bit is set to 0. 
 An interrupt occurs when the last byte is sent (the Send FIFO buffer is emptied) and an ACK is received.- MSS bit is set to 0
, or MSS and SCC bits are set to 1.
 
Figure 2-19 Master mode transmit interrupt 8 by enabling FIFO    (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0) 
 
  


P or SrACK Data ACK
DataACK
DataACK W
S Slave Address
 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if the Send FIFO buffer is emptied.   
- The send data is written in the Send FIFO buffer, and INT bit is set to 0. 
 An interrupt occurs when the last byte is sent (the Send FIFO buffer is emptied).   - MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
988 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-20 Master mode transmit interrupt 9 by enabling FIFO   (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0, NACK response) 
 
  


P or SrNACK Data ACK
DataACK
DataACK W
S Slave Address
 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if the Send FIFO buffer is emptied.   
- The send data is written in the Send FIFO buffer, and INT bit is set to 0. 
 An interrupt occurs when a NACK is responded.   - MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
 
Figure 2-21 Master mode interrupt 10 by disabling FIFO    (SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=0) 
 
  
 



P or SrACK DataACK
DataACK
DataACK W
S Slave Address 

 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is written in the TDR register. 
 An interrupt occurs when a single byte is sent and an ACK is received. - The send data is written in the TDR register. 
 An interrupt occurs when a single byte is sent and an ACK is received. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (TBI) is set, the TDRE bit is set to 1.
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
989 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-22 Master mode transmit interrupt 11 by disabling FIFO   (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0, ACK response) 
 
  
 
 
 
 




P or SrACK DataACK
DataACK
DataACK W
S Slave Address 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is written in the TDR register. 
 An interrupt occurs when a single byte is sent. - The send data is written in the TDR register. 
 An interrupt occurs when a single byte is sent. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (TBI) is set, the TDRE bit is set to 1. 
 
 
Figure 2-23 Master mode transmit interrupt 12 by disabling FIFO   
(SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0, NACK response) 
 
  




P or SrNACK DataACK
DataACK
DataACK W
S Slave Address 
  
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is written in the TDR register. 
 An interrupt occurs when a single byte is sent. - The send data is written in the TDR register. 
 An interrupt occurs when a single byte is sent. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT or TBI) is set, the TDRE bit is set to 1. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
990 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-24 Master mode transmit interrupt 13 by disabling FIFO (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0, NACK response during transmission) 
 
  
  



P or SrNACK DataACK
DataACK
DataACK W
S Slave Address 
 
  
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is written in the TDR register. 
 An interrupt occurs when a single byte is sent. - The send data is written in the TDR register. 
 An interrupt occurs when a NACK is responded. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT or TBI) is set, the TDRE bit is set to 1. 
 
Figure 2-25 Master mode transmit interrupt 14 by disabling FIFO    (SSR:DMA=1, IBCR:WSEL=1 -> 0, IBSR:RSA=0, ACK response) 
 
 
 



  
 
P or SrACK Data ACKData
ACK
DataACKW S Slave Address
 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received. 
- The send data is written in the send buffer. 
 An interrupt occurs when a single byte is sent. - The WSEL bit is set to 0 and the send data is written in the send buffer. 
 An interrupt occurs when a single byte is sent. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (TBIE) is set, the TDRE bit is set to 1. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
991 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-26 Master mode interrupt 15 by disabling FIFO   (SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=1) 
 
  
S ACK ACK Slave Address WDataACKDataACKData P or Sr
 
 
Figure 2-27 Master mode transmit interrupt 16 by enabling FIFO   
(SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=0, ACK response) 
 
 
 
 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address (reserved address) is sent, a direction bit is sent,   
and an ACK is received. - The send data is written in the TDR register, and the INT bit is set to 0. 
 An interrupt occurs when a single byte is sent and an ACK is received.    - The send data is written in the TDR register. 
 An interrupt occurs when a single byte is sent and an ACK is received. 
- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT or TBI) is set, the TDRE bit is set to 1. 
 


 
S Slave Address ACK ACK WDataACKDataACKData P or Sr
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs if the Send FIFO buffer is emptied.   
- The send data is written in the Send FIFO buffer. 
 An interrupt occurs when the last byte is sent (the Send FIFO buffer is emptied) and an ACK is received.- MSS bit is set to 0
, or MSS and SCC bits are set to 1. 
 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
992 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-28 Master mode transmit interrupt 17 by enabling FIFO   (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0) 
 
  
S ACK ACK W DataACKDataACKData P or SrSlave Ad
dress
  

 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs if the Send FIFO buffer is emptied. 
- The send data is written in the Send FIFO buffer. 
 An interrupt occurs when the last byte is sent (the Send FIFO buffer is emptied). - MSS bit is set to 0
, or both MSS and SCC bits are set to 1. 
 
Figure 2-29 Master mode transmit interrupt 18 by enabling FIFO    (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0, NACK response) 
 
  
S ACK W DataACKDataACKData P or SrSlave AddressNACK


 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs if the Send FIFO buffer is emptied.   
- The send data is written in the Send FIFO buffer. 
 An interrupt occurs when a NACK is responded.   - MSS bit is set to 0
, or both MSS and SCC bits are set to 1. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
993 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
   Data reception by the master 

 When DMA mode is disabled (SSR:DMA=0) 
When the data direction bit (R/W) is set to 1, the master receives data transmitted from a slave.   
When FIFO is disabled, the master operates as follows. 

 If the SSR:TDRE bit is set to 1, wait is generated (IBCR:INT=1, SSR:RDRF=1) each time one 
byte is received . At this time, an ACK or NACK re sponse is returned, according to the setting of the 
ACKE bit in the IBCR register, be fore wait if the IBCR:WSEL bit is 1, and after wait if the 
IBCR:WSEL bit is 0. 

 If the SSR:TDRE bit is set to 0, wait is not gene rated (IBCR:INT=0) when an ACK response is set 
for the ACKE bit in the IBCR register while wa it is generated when the NACK response is set 
(IBCR:INT=1). 
 
When FIFO is enabled, the SSR:RDRF  bit is set to 1 upon reception of data in the same number of bytes 
set for the number of bytes to be received. The interrupt  flag is set to 1 when the SSR:TDRE bit is 1, 
which puts the I
2C bus in the wait state. At this time, acknowl edgement operates as follows. Even if NACK 
is output, it is stored in receive FIFO as receive data. 

 In case of IBCR:WSEL=0, an NACK response is re turned when the SSR:TDRE bit is set to 1 if 
NACK is set for the ACKE bit. 

 In case of IBCR:WSEL=1, the interr upt flag is set to 1 after receiving the final byte, which generates 
wait. During that wait, an ACK or NACK response  is returned according to the IBCR:ACKE setting after 
the IBCR:ACKE bit is set and the interrupt flag is cleared to 0. 
 
For interrupt-generated wait, refer to the following. 
Table 2-6 IBCR:WSEL bit status for master data reception when DMA mode is disabled  (SSR:DMA=0) 
WSEL bit Operation 
0  After the second byte, after 
acknowledgement with 1 set for the SSR:TDRE bit, the 
interrupt flag (IBCR:INT) is set to 1  and SCL to LOW for the wait state. 
1 After the second byte, after the master has 
received one-byte data with 1 set for the 
SSR:TDRE bit, the interrupt flag (IBCR:INT) is set to 1 and SCL to LOW for the wait 
state. 
 
The following shows an ex ample procedure for receiving data from a slave. 

 When receive FIFO is disabled: 
1.
 Sets Slave Address (including the data direction  bit) to the TDR register and writes 1 to the 
IBCR:MSS bit.   
2.
 ACK is received after the Slave Addr ess setting is transmitted, and then the interrupt flag (IBCR:INT) 
is set to 1. 
3.
 Writes 0 to the interrupt flag bit (IBCR:INT) u pon updating of the IBCR:WSEL bit to release the 
wait state of the I2C bus. 
4.
 After receiving one byte, sets the in terrupt flag to 1 to set the I2C bus in the wait state after 
transmitting acknowledgment in  case of IBCR:WSEL=0 and directly after receiving one byte in 
case of IBCR:WSEL=1. Repeats steps 3 to 4 until all the specified number of data sets have been 
received. 
5.
 After receiving the last data, outputs NACK and sets  the IBCR:MSS bit to 0 or sets the IBCR:SCC 
bit to 1 to generate the stop condition or iteration start condition. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
994 
MB9Axxx/MB9Bxxx  Series