Fujitsu Series 3 Manual

							 
1. Overview of the Multi-function Serial Interface 
 
CHAPTER: Multi-function Serial Interface 
This chapter describes the overview of the multi-function serial interface. 
 
1.
 Overview of the Multi-function Serial Interface 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFMFS-E01.2 
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CHAPTER  19-1: Multi-function  Serial Interface 
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1. Overview of the Multi-function Serial Interface 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Multi-function Serial Interface 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  3 
1.  Overview of the Multi-function Serial Interface 
This multi-function serial interface has the following characteristics. 
  Interface Mode 
The following interface modes are  selectable for the multi-function serial interface depending on the 
operation mode settings. 
   UART0 (Asynchronous normal serial interface) 
   UART1 (Asynchronous multi-processor serial interface) 
   CSIO (Clock synchronous serial interface) (SPI can be supported) 
   LIN(LIN bus interface) 
   I
2C (I2C bus interface) 
 
See explanations of each chapter for details about each interface. 
 
  Switching the Interface Mode 
To communicate through each serial interface,  the serial mode register (SMR) shown in Ta b l e  1 - 1 should be 
used to set the o
peration mode before starting the communication. 
Table 1-1 Switching Interface Mode 
MD2 MD1 MD0 Interface mode 
0  0  0 UART0 (Asynchronous normal serial interface) 
0  0  1 UART1 (Asynchronous multi-processor serial interface) 
0  1  0 CSIO (Clock synchronization serial interface) (SPI can be supported) 
0  1  1 LIN(LIN bus interface) 
1 0  0 I2C (I2C bus interface) 
 
 
  Transmission and reception cannot be guaranteed when the operation mode is switched while one of the 
serial interfaces is still in use for transmission or reception operation. 
   To switch the current operation m ode, issue a programmable clear in struction (SCR:UPCL=1) or disable 
the I
2C (ISMK:EN=0) , and switch the operation mode continuously. 
   The settings not listed in  Ta b l e  1 - 1 are prohibited. 
 
  Transmission/Reception FIFO 
This UART has a 16-byte transmission FIFO and 16- byte reception FIFO. The FIFO steps should be 
converted to 16 bytes when reading through this text. 
  LIN Sync field Detection: LSYN 
If you are to use an ICU in the LIN bus interf ace mode, use the ICU of the multifunction timer. 
For switching an input to an ICU, see the section fo r Extended Function Pin Setting Register in the chapter 
I/O PORT. 
CHAPTER  19-1: Multi-function  Serial Interface 
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1. Overview of UART (Async Serial Interface) 
 
CHAPTER: UART (Async Serial Interface) 
This chapter explains the UART (async serial interface) function supported in operation mode 
0 and 1 of the multifunctional serial interface. 
 
1.
 Overview of UART (Async Serial Interface) 
2. UART Interrupt 
3. UART Operation 
4. Dedicated Baud Rate Generator 
5. Setting Procedure and Program Flow in Operation Mode 0 (Async Normal Mode) 
6. Setting Procedure and Program Flow in Oper ation Mode 1 (Async Multiprocessor Mode) 
7. UART (Async Serial Interface) Registers 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FM15U-E05.2 
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CHAPTER  19-2: UART  \050Async  Serial Interface\051 
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1. Overview of UART (Async Serial Interface) 
 
1.  Overview of UART (Async Serial Interface) 
UART (async serial interface) is a general-purpose serial data communications interface for 
asynchronous communications with external devices. It supports a bi-directional 
communications function (normal mode) and a master/slave type communications function 
(multi-processor mode: both master and slave modes supported). It also has transmit/receive 
FIFO installed.
 
  Functions of UART (Async Serial Interface) 
 
   Function 
1 Data 
  Full duplex double buffer (when FIFO is not used) 
   Transmit/receive FIFO (size:  max 128 × 9 bits each)*1 (when FIFO 
is used) 
2 Serial  input Run oversampling three times with 
the bus clock and determine the 
value of received data based on the majority sampling value. 
3 Transfer system  Asynchronous 
4 Baud rate 
  Complete with a dedicated baud rate generator (constructed with a 
15-bit reload counter) 
   The external clock input can be ad justed with the reload counter. 
5 Data length 
  5-9 bits (in normal mode)/7 or 8 bits (in multiprocessor mode) 
6  Signaling system  NRZ (Non Return to Zero), inverted NRZ 
7 Start bit detection  
  In synch with the falling edge of the start bit (in the NRZ system) 
   In synch with the rising edge of the start bit (in the inverted NRZ 
system) 
8 Receive erro r detection 
  Framing error 
   Overrun error 
   Parity error*2 
9 Hardware flow control  CTS/RTS-based automatic transmission/reception control 
10 Interrupt request  
  Receive interrupt 
(upon reception completed, framing error, overrun error or parity 
error
*2) 
   Transmit interrupts (transmit data empty, transmit bus idle) 
   Transmit FIFO interrupt (when transmit FIFO is empty) 
   For both transmission and reception, the extended intelligent I/O 
service (EIIOS) and the DM A function are available. 
11 Master/slave communications 
functions 
  (in multiprocessor mode)  One (master)-to-n (slaves) communication is enabled.   
(Both master and slave systems are supported.) 
12 FIFO options  
  Transmit/receive FIFO installed (maximum capacity: 128 × 9 bits   
for transmit FIFO, 128 bytes × 9 bits for receive FIFO) 
*1  
   Transmit FIFO or receive FIFO can be selected. 
   Transmit data can be resent. 
   Receive FIFO interrupt timing  can be changed via software. 
   FIFO resetting is supported independently. 
*1: The FIFO capacity size varies from model type to model type. 
*2: Parity errors are only generated in normal mode. 
 
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2. UART Interrupt 
 
2. UART Interrupt 
UART generates transmit or receive interrupts. These interrupt requests can be generated if: 
- Incoming data is set in the Receive Data Register (RDR) or a data receive error occurs. 
- Outgoing data is transferred from the Transmit Data Register (TDR) to the transmit shif
t 
register and the data transmission is started. 
- The transmit bus is idle (No data transmission occurs). 
- Transmit FIFO data is requested. 
  UART Interrupt 
Ta b l e  2 - 1  shows the relationships between the UART inte rrupt control bits and  the interrupt causes. 
Table 2-1 UART interrupt control bits and interrupt causes 
Operation 
mode Interrupt type  Interrupt 
request 
flag  Bit  Flag 
register 
0 1  Interrupt cause 
Interrupt 
cause 
enable bit Operation to clear  
interrupt request flag 
A single-byte 
reception 
Reading from the received data 
register (RDR) 
Reception of a data 
volume matching the 
value set for FBYTE. 
RDRF SSR 
  
While the FRIIE bit is 
1 and the receive 
FIFO contains valid 
data, a receive idle 
state continues for 8 
bits or longer period.  Reading from the Received Data 
Register (RDR) until receive FIFO 
is emptied 
ORE SSR 
  Overrun error 
FRE SSR 
  Framing error 
Reception 
PE SSR   x Parity error  SCR:RIE 
Setting the reception error flag clear 
bit (SSR:REC) to 1   
TDRE SSR    The Transmit Data 
Register is empty 
SCR:TIE Writing to the Transmit Data 
Register (TDR) or setting the 
transmit FIFO operation enable bit 
to 1 when the transmit FIFO 
operation enable bit is set to 0 and 
valid data are present in transmit 
FIFO (re-transmitting data) 
*1 
TBI SSR 
  No data transmission SCR:TBIE Writing to the Transmit Data 
Register (TDR) or setting the 
transmit FIFO operation enable bit 
to 1 when the transmit FIFO 
operation enable bit is set to 0 and 
valid data are present in transmit 
FIFO (re-transmitting data) 
*1 
Transmission 
FDRQ FCR1    Transmit FIFO is 
empty. 
FCR1:FTIEThe FIFO transmit data request bit 
(FCR1:FDRQ) is set to 0 or 
transmit FIFO is full. 
*1: Set the TIE bit to 1 only after the TDRE bit has been set to 0.   
 
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2. UART Interrupt 
 
2.1.  Receive interrupt and flag set timing 
Data reception can be interrupted by a Receive Completion (SSR:RDRF) or a Receive Error 
Occurrence (SSR:PE, ORE, FRE). 
 Receive interrupt and flag set timing   
Upon detection of the first  stop bit, received data are stored in the Receive Data Register (RDR). When the 
data reception is completed (SSR:RDRF=1) or when  a data receive error occurs (SSR:PE, ORE, FRE=1), 
each flag is set. If receive interrupts are enab led (SSR:RIE=1) then, a receive interrupt occurs. 
 
If a receive e r

ror occurs, data in the Recei ve Data Register (RDR) becomes  invalid. 
 
Figure 2-1 RDRF (Receive Data Register Full) flag bit set timing    
Receive data
RDRFST D0 D1 D2 D5 D6 D7 SP ST
A receive interrupt occurred.
 
  
 
Figure 2-2 FRE (Framing Error) flag bit set timing   
 
Receive data
RDRF
Precautions: - If the first stop bit is LOW, a framing error occurs.
- The RDRF bit is set to 1 and data can be received even if a framing error has occurred .  However, the received data is invalid. ST D0 D1 D2 D5 D6 D7 SP
ST
A receive interrupt occurred.
FRE
  
 
  During reception, if the  foll

owing is detected at the same time as the st op bit sampling point 
 or before the 
1-2 bus clock, the relevant edge becomes invalid, whic h may disable normal reception of the next data. To 
output frames continuously, adequate intervals are required between frames. 
  The falling edge of serial data (When ESCR:INV=0) 
   The rising edge of serial data (When ESCR:INV=1) 
 
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2. UART Interrupt 
 
Figure 2-3 ORE (Overrun Error) flag bit set timing 
 
Receive data
RDRFORE
   
ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP
Precautions: - If the next data is transferred before the receive data is read  (RDRF=1), an overrun error occurs.
 
  
  
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2. UART Interrupt 
 
2.2.  Interrupt and flag set timing when receive FIFO is used 
If the receive FIFO is used, an interrupt occurs when the FBYTE data (preset for the FBYTE 
register) is received. 
 Interrupt and flag set timing  when receive FIFO is used 
If the receive FIFO is used, an interrupt occurs depending on the value set for the FBYTE register.   
  When full FBYTE data is received, the receive data full flag (SSR:RDRF) of the Se rial Status register is 
set to 1. If receive interrupts are enabled (SCR:RI E) during this time, a receive interrupt occurs. 
   If both of the following conditions are satisfied and if the receive idle state continues for more than 8 
baud rate clocks, the interrupt flag (SSR:RDRF) is set to 1. 
  The receive FIFO idle detection  enable bit (FCR:FRIIE) is 1. 
   The number of data sets stored in the recei ve FIFO does not reach the transfer count. 
If the RDR data is read during counting of 8 clocks, this counter is reset to 0, and counting for 8 
clocks is restarted. If receive FIFO is disabled, this  counter is reset to zero (0).If data remains in the 
receive FIFO and if receive FIFO is en abled, the data counting is restarted. 
   When data is read from the Receive Data Register  (RDR) until receive FIFO is emptied, the receive data 
full flag (SSR:RDRF) is cleared. 
   If the valid receive data amount is the same as the FI FO capacity and if the next data is received, an 
overrun error (SSR:ORE=1) occurs. 
 
Figure 2-4 Receive interrupt timing when Receive FIFO is used 
 
Receive data
FBYTE setting 
(with the transfer count)
RDRF
1st byte  
3
An interrupt occurs when the FBYTE (transmit 
data) count matches the receive data count.  
 
Data reading from RDR
2nd byte   3rd byte   4th byte  
ST  SP  ST  SP  ST  SP  ST   SP  ST  5th byte  SP  
All receive data are read.  
012 Reading of FBYTE 
(Effective byte count display)321 0 1 2
  
 
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2. UART Interrupt 
 
Figure 2-5 ORE (Overrun Error) flag bit set timing 
 
Receive data
FBYTE setting 
(with the transfer count)
RDRF
62nd byte
62
Precautions:
If the next data set is received when the FBYTE reading is indicating the FIFO capacity, 
an overrun error occurs.
This figure shows a case where a 64-byte FIFO capacity is applied.
63rd byte 64th byte 65th byte
STSPST SP STSP ST SP ST66th byteSP
62 64Reading of FBYTE 
(Effective byte count display)
ORE
An overrun error occurred. 
63
 
 
 
 
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CHAPTER  19-2: UART  \050Async  Serial Interface\051 
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2. UART Interrupt 
 
2.3.  Transmit interrupt and flag set timing 
A transmit interrupt occurs when outgoing data is transferred from the Transmit Data Register 
(TDR) to the transmit shift register (SSR:TDRE = 1) and transmission starts and when no 
transmission is performed (SSR:TBI = 1).   
 Transmit interrupt and flag set timing 
  Transmit data empty flag (SSR:TDRE) set timing 
After data has been transferred from the Transmit Data  Register (TDR) to the transmit shift register, the 
next data can be written in the TDR (SSR:TDRE = 1). If transmit interrupts are enabled (SCR:TIE = 1) 
during this time, a transmit interrupt occurs. As the SSR:TDRE bit is read only, the SSR:TDRE bit is 
cleared to 0 when data is written to the Transmit Data Register (TDR). 
Figure 2-6 Transmit data empty flag (SSR:TDRE) set timing 
 
Transmit data 
(Mode 0 or 1)
TDRE
Data writing in TDR
ST D0 D1 D2 D3
A transmit interrupt occurred.A transmit interrupt occurred.
D4 D5 D6 D7 SP ST D0 D1 D2
ST : Start bit D0 - D7 : Data bits SP : Stop bit  
 
 Transmit bus idle flag (SSR:TBI) set timing 
If the Transmit Data Register is empty (SSR:TDRE=1) an d no data is transmitted, the SSR:TBI bit is set to 
1. If transmit bus idle interrupts are enabled (SCR:TBIE  = 1) during this time, a transmit interrupt occurs. 
When transmit data is written to the Transmit Data  Register (TDR), both the SSR:TBI bit and the transmit 
interrupt request are cleared. 
Figure 2-7 Transmit bus idle flag (TBI) set timing 
 
Transmit data
TBI
Writing in TDR
ST
A transmit interrupt by 
the TBI bit occurred.TDRE
ST : Start bit D0 - D7 : Data bits SP : Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 SP D0 D1 D2 D3 D4 D5 D6 D7 ST
 
 
 
 
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CHAPTER  19-2: UART  \050Async  Serial Interface\051 
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