Fujitsu Series 3 Manual

							 
4. CAN Registers 
 
4. CAN Registers 
The following registers are provided for CAN. 
- CAN Control Register (CTRLR) 
- CAN Status Register (S
TATR) 
- CAN Error Counter (ERRCNT) 
- CAN Bit Timing Register (BTR) 
- CAN Interrupt Register (INTR) 
- CAN Test Register (TESTR) 
- CAN Prescaler Extension Register (BRPER) 
- IFx Command Request Register (IFxCREQ) 
- IFx Command Mask Register (IFxCMSK) 
- IFx Mask Registers 1, 2 (IFxMSK1, IFxMSK2) 
- IFx Arbitration 1, 2 (IFxARB1, IFxARB2) 
- IFx Message Control Register (IFxMCTR) 
- IFx Data Register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) 
- CAN Transmit Request Registers 1, 2 (TREQR1, TREQR2) 
- CAN New Data Registers 1, 2 (NEWDT1, NEWDT2) 
- CAN Interrupt Pending Registers 1, 2 (INTPND1, INTPND2) 
- CAN Message Valid Registers 1, 2 (MSGVAL1, MSGVAL2) 
  Total control register list 
Table 4-1 Total control register list 
Abbreviation Register name See 
CTRLR CAN  Control Register  4.2.1 
STATR CAN Status Register  4.2.2 
ERRCNT CAN Error Counter  4.2.3 
BTR CAN Bit Timing Register  4.2.4 
INTR CAN Interrupt Register  4.2.5 
TESTR CAN Test Register  4.2.6 
BRPER CAN Prescaler Extension Register  4.2.7 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1215 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. CAN Registers 
 
 Message interface register list 
Table 4-2 Message interface register list 
Abbreviation Register name See 
IF1CREQ  IF1 Command Request Register  4.3.1 
IF1CMSK IF1 Command Mask Register  4.3.2 
IF1MSK1 IF1 Mask Register 1  4.3.3 
IF1MSK2 IF1 Mask Register 2  4.3.3 
IF1ARB1 IF1 Arbitration Register 1  4.3.4 
IF1ARB2 IF1 Arbitration Register 2 4.3.4 
IF1MCTR IF1 Message Control Register  4.3.5 
IF1DTA1 IF1 Data A Register 1 (Little endian)  4.3.6 
IF1DTA2 IF1 Data A Register 2 (Little endian)  4.3.6 
IF1DTB1 IF1 Data B Register 1 (Little endian)  4.3.6 
IF1DTB2 IF1 Data B Register 2 (Little endian)  4.3.6 
IF1DTA2 IF1 Data A Register 2 (Big endian)  4.3.6 
IF1DTA1 IF1 Data A Register 1 (Big endian)  4.3.6 
IF1DTB2 IF1 Data B Register 2 (Big endian)  4.3.6 
IF1DTB1 IF1 Data B Register 1 (Big endian)  4.3.6 
IF2CREQ IF2 Command Request Register  4.3.1 
IF2CMSK IF2 Command Mask Register  4.3.2 
IF2MSK1 IF2 Mask Register 1  4.3.3 
IF2MSK2 IF2 Mask Register 2  4.3.3 
IF2ARB1 IF2 Arbitration Register 1  4.3.4 
IF2ARB2 IF2 Arbitration Register 2 4.3.4 
IF2MCTR IF2 Message Control Register  4.3.5 
IF2DTA1 IF2 Data A Register 1 (Little endian)  4.3.6 
IF2DTA2 IF2 Data A Register 2 (Little endian)  4.3.6 
IF2DTB1 IF2 Data B Register 1 (Little endian)  4.3.6 
IF2DTB2 IF2 Data B Register 2 (Little endian)  4.3.6 
IF2DTA2 IF2 Data A Register 2 (Big endian)  4.3.6 
IF2DTA1 IF2 Data A Register 1 (Big endian)  4.3.6 
IF2DTB2 IF2 Data B Register 2 (Big endian)  4.3.6 
IF2DTB1 IF2 Data B Register 1 (Big endian)  4.3.6 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1216 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. CAN Registers 
 
 Message handler register list 
Table 4-3 Message handler register list 
Abbreviation Register name See 
TREQ1  CAN Transmit Request Register 1  4.5.1 
TREQ2 CAN Transmit Request Register 2  4.5.1 
NEWDT1 CAN New Data Register 1  4.5.2 
NEWDT2 CAN New Data Register 2  4.5.2 
INTPND1 CAN Interrupt Pending Register 1  4.5.3 
INTPND2 CAN Interrupt Pending Register 2  4.5.3 
MSGVAL1 CAN Message Valid Register 1  4.5.4 
MSGVAL2 CAN Message Valid Register 2  4.5.4 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1217 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. CAN Registers 
 
4.1.  CAN register functions 
An address space of 256 bytes is allocated the CAN register. The CPU gains access to the 
message RAM via the message interface registers. 
This section lists CAN registers, and describes the detailed function of each register. 
 Total control registers 
  CAN Control Register (CTRLR) 
   CAN Status Register (STATR) 
   CAN Error Counter (ERRCNT) 
   CAN Bit Timing Register (BTR) 
   CAN Interrupt Register (INTR) 
   CAN Test Register (TESTR) 
   CAN Prescaler Extension Register (BRPER) 
 Message interface registers 
  IFx Command Request Register (IFxCREQ) 
   IFx Command Mask Register (IFxCMSK) 
   IFx Mask Registers 1, 2 (IFxMSK1, IFxMSK2) 
   IFx Arbitration 1, 2 (IFxARB1, IFxARB2) 
   IFx Message Control Register (IFxMCTR) 
   IFx Data Register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) 
 Message handler registers 
  CAN Transmit Request Registers 1, 2 (TREQR1, TREQR2) 
   CAN New Data Registers 1, 2 (NEWDT1, NEWDT2) 
   CAN Interrupt Pending Registers 1, 2 (INTPND1, INTPND2) 
   CAN Message Valid Registers 1, 2 (MSGVAL1, MSGVAL2) 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1218 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. CAN Registers 
 
4.2.  Total control registers 
Total control registers control the CAN protocol and operating modes, and p\
rovide status 
information. 
 Total control registers 
  CAN Control Register (CTRLR) 
   CAN Status Register (STATR) 
   CAN Error Counter (ERRCNT) 
   CAN Bit Timing Register (BTR) 
   CAN Interrupt Register (INTR) 
   CAN Test Register (TESTR) 
   CAN Prescaler Extension Register (BRPER) 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1219 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. CAN Registers 
 
4.2.1. CAN Control Register (CTRLR) 
The CAN Control Register controls the operating modes of the CAN controller. 
 Register configuration 
- CAN Control Register (high-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Control Register (low-order byte)  bit  7 6 5  4 3 2 1 0 
Field Test  CCE DAR Reserved EIE SIE  IE Init 
Attribute  R/W R/W R/W  R0,W0 R/W R/W  R/W R/W 
Initial value 0 0 0  0 0 0 0 1 
 
  Register functions 
[bit 15:8] Reserved bits 
Reserved bits are read as 0, an d must be set to 0 when writing. 
[bit 7] Test: Test mode enable bit 
Bit Function 
0  Normal operation         [Initial value] 
1 Test mode 
 
 
The T

est bit can be set to 1 only while the Init bit is 1. 
 [bit 6] CCE: Bit Timing Register write enable bit 
Bit Function 
0  Disables write access to the CAN Bit Timing Register and CAN Prescaler 
Extension Register.       [Initial value] 
1 Enables write access to the CAN Bit Timing Register and CAN Prescaler 
Extension Register. This setting is valid while the Init bit is 1. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1220 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. CAN Registers 
 
[bit 5] DAR: Automatic retransmission disable bit 
Bit Function 
0 Enables automatic retransmission when arbitration is lost or an error is detected. 
[Initial value] 
1 
Disables automatic retransmission. 
 
Based on the CAN specification (ISO11898. See 6.3.3 Recovery Sequence), the CAN controller 
automatically resends frames when arbitration is lost or  an error is detected during transfer. To allow the 
automatic retransmission, set the DAR bit to 0.  To operate CAN in Time Triggered CAN (TTCAN. See 
ISO11898-1) environments, set the DAR bit to 1. 
 
 
  In the m o

de where the DAR bit is set to 1, the TxRqst bit and the NewDat bit of a message object 
behave dif f

erently. (For message objects, see  4.4 Message objects ) 
   When frame  tran

smission has started, the TxRqst bit of the message object is reset to 0 while 
NewDat remains set. 
   When frame transmission has finished successfully, the NewDat bit is reset to 0. 
If arbitration is lost or an error is detected during transmission, the NewDat bit remains set. 
To restart the transmission, the CPU must set the TxRqst to 1. 
   If the DAR bit in the CAN Control Register (CTRLR) is changed from 0 to 1 during frame 
transmission (TxRqst = 1), a frame being transmitted  will be transmitted again. Therefore, change the 
DAR bit only while the Init bit is 1. 
   A transmission using two or more message buffers while the DAR bit is set to 1 assumes the following 
operations: 
  If the TxRqst in other message buffer is set to 1 before or during frame transmission (TxRqst bits 
in multiple message buffers are set to 1), all the set TxRqst bits are reset to 0 upon the start of 
frame transmission, and data in the message buffer with the highest priority will be sent. 
 
When frame transmission has finished successfully, the NewDat bit of the sent message buffer is 
reset to 0 and, if TxIE of the message buffer is 1  then, IntPnd of the message object is set to 1. 
Data in other message buffers will not be sent because their TxRqst bits have been reset to 0 upon 
the start of frame transmission. 
Check the message buffer sent by NewDat and IntP nd, and then set TxRqst and NewDat to 1 again 
for another message buffer to be sent. 
 
[bit 4] Reserved bit  Reserved bits are read  as 0

, and must be set to 0 when writing. 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1221 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. CAN Registers 
 
[bit 3] EIE: Error interrupt code enable bit 
Bit Function 
0 A change of the BOff or EWarn bit in th
e CAN Status Register disables the setting 
of interrupt code in the CAN Interrupt Register. 
[Initial value] 
1  A change of the BOff or EWarn bit in th
e CAN Status Register enables the setting 
of status interrupt code in the CAN Interrupt Register. 
 
[bit 2] SIE: Status interrupt code enable bit 
Bit Function 
0  A change of the TxOk, RxOk, or LEC bit in the CAN Status Register disables the 
setting of interrupt code in the CAN Interrupt Register. 
[Initial value] 
1 A change of the TxOk, RxOk, or LEC bit in the CAN Status Register enables the 
setting of status interrupt code in the CAN Interrupt Register. A change of TxOk, 
RxOk, or LEC bit caused by write access 
from the CPU is not set in the CAN 
Interrupt Register. 
 
[bit 1] IE: Interrupt enable bit 
Bit Function 
0  Disables interrupt generation. [Initial value] 
1 Enables interrupt generation. 
 
[bit 0] Init: Initialization bit 
Bit Function 
0  CAN controller can operate.   
1 Initialization     [Initial value] 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1222 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. CAN Registers 
 
   The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or 
resetting the 

Init bit. If the device enters busoff state, the CAN controller itself sets the Init bit to 1, 
stopping all bus operations. If the Init bit is cleared to 0 from the busoff state, the bus operation 
remains stopped until 129 bus idle sequences (one bus  idle sequence consists of 11 recessive bits) occur 
consecutively. When the bus recovery sequence  has completed, the error counter is reset. 
   If the Init bit is set to 1 and then reset to 0 during the busoff recovery sequence, the busoff recovery 
sequence restarts from the beginning (sends  a set of 11 recessive bits 129 times). 
   To write to the CAN Bit Timing Register, set the Init and CCE bits to 1. 
   Setting the Init bit to 1 during transf er stops data reception immediately. 
   Before making transition to low consumption mode  (stop mode or clock mode), and before changing 
clock supply, the Init bit must be set to 1 to initialize the CAN controller. 
   To change the division ratio of clock supplied to the CAN interface by using the following registers, set 
the Init bit to 1 to stop the CAN controller previously. 
   CAN Bit Timing Register (BTR) 
   CAN Prescaler Extension Register (BRPER) 
   CAN Prescaler (CANPRE) 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1223 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. CAN Registers 
 
4.2.2. CAN Status Register (STATR) 
The CAN Status Register indicates the CAN status and a CAN bus state. 
 Register configuration 
- CAN Status Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Status Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field BOff  EWarn EPass RxOk  TxOk  LEC 
Attribute R,WX R,WX R, WX R,W R,W R,W  R,W R,W 
Initial value 0 0 0  0 0 0 0 0 
 
  Register functions 
[bit 15:8] Reserved bits 
Reserved bits are read as 0, an d must be set to 0 when writing. 
[bit 7] BOff: Busoff bit 
Bit Function 
0  CAN bus is not in busoff state. 
[Initial value] 
1 
CAN bus is in busoff state. 
 
[bit 6] EWarn: Warning bit 
Bit Function 
0  Both the send and receive counters are below 96. 
[Initial value] 
1 
Send or receive counter ha s reached or exceeded 96. 
 
[bit 5] EPass: Error passive bit 
Bit Function 
0  Both the send and receive counters are below 128 (error active state). 
[Initial value] 
1 The RP bit of the receive counter is 1,
 or the send counter is between 128 and 
255 (error passive state). 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-2: CAN Controller 
MN706-00002-1v0-E 
1224 
MB9Axxx/MB9Bxxx  Series