Fujitsu Series 3 Manual

							 
9. Descriptions of base timer functions 
 
9.1.9. Timer  Register  (TMR) 
The Timer Register (TMR) reads the value of the 16-bit down counter. 
 bit 15       0 
Field TMR [15:0] 
Attribute R 
Initial value  0x0000 
 
The value of the 16-bit down counter is read. 
   Access the TMR register with 16-bit data. 
 
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9. Descriptions of base timer functions 
 
9.2.  PPG timer function 
The function of the base timer can be set to either the 16-bit PWM timer, 16-bit PPG timer, 
16/32-bit reload timer, or 16/32-bit PWC timer using the FMD2, 1, and 0 bits in the Timer 
Control Register. This section explains the timer functions available when PPG is set. 
1. 16-bit PPG timer operations 
2.  Continuous operation 
3.  One-shot operation 
4.  Interrupt causes and timing chart 
5.  PPG timer operation flowchart 
6.  Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PPG 
timer is selected 
7.  LOW

 Width Reload Register (PRLL) 
8.  HIGH Width Reload Register (PRLH) 
9.  Timer Register (TMR) 
 
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9. Descriptions of base timer functions 
 
9.2.1. 16-bit PPG timer operations 
In PPG timer operations, any output pulse can be controlled by setting the LOW and HIGH 
widths of the pulse in respective reload registers. 
 Overview of operations 
Two 16-bit long reload registers for setting the LOW and HIGH widths, respectively, and one buffer for 
setting the HIGH width are used (PRLL, PRLH, and PRLHB). 
A start trigger initially causes the PRLL set value to be  loaded to the 16-bit down counter and, at the same 
time, the PRLH set value to be transferred to the PRLHB. The PPG timer changes the output level to LOW 
and counts down for every count clock. Upon detection of an underflow, the PPG timer reloads the PRLHB 
value to the counter, inverts the PPG output waveforms, and continues to count down. At the next detection 
of an underflow, it inverts the PPG output waveforms,  reloads the PRLL set value to the counter, and 
transfers the PRLH set value to the PRLHB. 
This operation causes the output waveform to be pulse output having LOW and HIGH widths 
corresponding to the values in  the respective reload registers. 
 Timing of writing to the reload registers 
Data writing to the PRLL and PRLH reload registers occu rs upon detection of a start trigger and during the 
period from when an underflow interrupt cause (UDIR)  is set to when the next cycle starts. The data set 
here is used as the setting for the next cycle. The items of data set in the PRLL and PRLH are automatically 
transferred to the TMR and PRLHB, respectively, when a start trigger is  detected and when an underflow 
occurs at the completion of HIGH width counting. Th e data transferred to the PRLHB is automatically 
reloaded to the TMR when an underflow occurs at the completion of LOW width counting. 
 
Rising edge detection
Trigger
PPG output waveform
PRLLL3  
L
0  
IRQ1 
(TGIR cause)
IRQ0
 (TGIR cause)
L1  
L
2  
PRLHH
3 
H
0 H
1 H
2 
PRLHB0xXXXX H
0 
H
1 H
2 
TMR
0xXXXX    to 
0x0000    to 
 
0x0000    
 to
 
 
H0 
L
0  L
1  
H
1 
Sets the LOW and HIGH widths 
of the next cycle in the register.
L 2  H
2 
H
0 H
1 H
2
0x0000
L   to 0x0000
0 L   to 0x0000
1 L   to 0x0000
2
  
 
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9. Descriptions of base timer functions 
 
9.2.2. Continuous  operation 
In continuous operations, any pulse can be output continuously by updating the LOW and 
HIGH widths at the set timing of each interrupt cause. When a restart is enabled, the counter 
is reloaded when an edge is detected during operation. 
 Continuous operation 
  When a restart is disabled (RTGEN = 0) 
Figure 9-8 PPG operation timing chart (when a restart is disabled) 
 
Rising edge detection
The trigger is ignored.
Trigger
m
n
o
(1) (2)
 
PPG output 
waveform  
Interrupt Start edge
TGIR
UnderflowUDIRUnderflowUDIR
(1) = T(m+1)ms
(2) = T(n+1)ms T : Count clock cycle
m : PRLL value
n : PRLH value
  

 When a restart is enabled (RTGEN = 1) 
Figure 9-9 PPG operation timing chart (when a restart is enabled) 
 
Rising edge detection
Restarted by the trigger
Trigger
m
n
o
(1) (2)
 
PPG output 
waveform
(1) = T(m+1)ms
(2) = T(n+1)ms T : Count clock cycle
m: PRLL value
n: PRLH value
  
 
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9. Descriptions of base timer functions 
 
9.2.3. One-shot  operation 
In one-shot operation, a single pulse of any width can be output using a trigger. When a 
restart is enabled, the counter is reloaded when an edge is detected during operation. 
 One-shot operation 
  When a restart is disabled (RTGEN = 0) 
Figure 9-10 One-shot operation timing chart (trigger restart is disabled) 
 
Rising edge detection
The trigger is ignored.
Trigger
m
n
o
(1) (2)
 
PPG output 
waveform
(1) = T(m+1)ms
(2) = T(n+1)ms T : Count clock cycle
m : PRLL value
n: PRLH value
  

 When a restart is enabled (RTGEN = 1) 
Figure 9-11 One-shot operation timing chart (trigger restart is enabled) 
 
Rising edge detection
Restarted by the trigger
Trigger
m
n
o
(1)
(2)
PPG output 
waveform
(1) = T(m+1)ms
(2) = T(n+1)ms T : Count clock cycle
m: PRLL value
n: PRLH value
  
 
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9. Descriptions of base timer functions 
 
 Relation between reload value and pulse width 
The output pulse width is equal to the 16-bit long reload register value added by 1, and which is multiplied 
by the count clock cycle. Therefore, when the reload register value is 0x0000, the pulse width is equal to 
one count clock cycle. When the relo ad register value is 0xFFFF, the pulse width is equal to 65536 count 
clock cycle. The pulse width calcul ation formulas are as follows: 
PL = T x (L + 1)  PL  :  Width of LOW pulse 
PH = T x (H + 1)  PH  :  Width of HIGH pulse    T  :  Count clock cycle 
 L : PRLL value 
 H : PRLH value 
 
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CHAPTER  14-2: Base Timer 
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9. Descriptions of base timer functions 
 
9.2.4. Interrupt causes and timing chart 
This section explains interrupt causes and a timing chart. 
 Interrupt causes and timing chart (PPG output: Normal polarity) 
As a time from trigger input to loading of the counter va lue, T is required for software triggering or 2T to 
3T (T: machine cycle) fo r external triggering. 
Interrupt causes are set to detection of a PPG star t trigger and an underflow in HIGH level output. 
Figure 9-12  shows the interrupt cause and a timing chart where LOW width set value = 1 and HIGH width 
set v alue = 1
.

 
Figure 9-12 Interrupt causes and timing chart of the PPG timer 
 
2T to 3T (External trigger)
Trigger
Load
Count clock
Count value
PPG output 
waveform
Interrupt
0X0001  0x0001
 
0x0000
 0x0000
 0x0001 0x0000
Start edge TGIR
UnderflowUDIR
0xXXXX
  
 
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9. Descriptions of base timer functions 
 
9.2.5. PPG timer operation flowchart 
This section provides an operation flowchart of the PPG timer. 
 PPG timer operation flowchart 
 
  
PPG mode selectio
n
Count clo ck 
 selection
Operation mode selection
Interrupt flag clea
r
Interrupt enable
Settings 
Stop of count operation
Stop of operation
Continuous operation
Trigger detection 
TGIR flag setting
Start of decrement
Occurrence of an underflow UDIR flag setting
MDSE =0 ?  
No  
Yes
PPGL output
PPGH output
shot operation
-
One
Start by the CTEN bit
 
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CHAPTER  14-2: Base Timer 
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9. Descriptions of base timer functions 
 
9.2.6. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PPG 
timer is selected 
The Timer Control Register (TMCR) controls the PPG timer. Note that some bits cannot be 
rewritten while the PPG timer is in operation. 
 Timer Control Register (H igh-order bytes of TMCR) 
 
bit 15 14 13 12 11 10 9 8 
Field res CKS2 CKS1 CKS0 RTGENPMSK EGS1 EGS0 
Attribute  R/W R/W  R/W R/W R/W R/W R/W R/W 
Initial value 0 0  0 0 0 0 0 0 
 
[bit 15] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 14:12, TMCR2: bit 8] CKS3 to CKS0: Count clock selection bit    Select the count clock for the 16-bit down counter. 
   Changes to the count clock setting are applied immediately. For this reason, changes to CKS3 through 
CKS0 must be made when the counting is stopped (CTEN = 0). However, it is possible to make 
changes at the same time you set 1 to the CTEN bit. 
CKS3 CKS2 CKS1 CKS0 Description 
0 0 0 0 
 
0 0 0 1 
 /4 
0 0 1 0 
 /16 
0 0 1 1 
 /128 
0 1 0 0 
 /256 
0 1 0 1  External clock (rising edge event) 
0 1 1 0 External clock (falling edge event) 
0 1 1 1  External clock (both edge event) 
1 0 0 0 
 /512 
1 0 0 1 
 /1024 
1 0 1 0 
 /2048 
Others Setting  disabled 
 
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9. Descriptions of base timer functions 
 
[bit 11] RTGEN: Restart enable bit This bit enables restart by a software trigger or trigger input. 
Bit Description 
0 Restart  disabled 
1 Restart  enabled 
 
[bit 10] PMSK: Pulse output mask bit    This bit controls the output level of PPG output waveforms. 
   When this bit is set to 0, PPG waveforms are output as they are. 
   When this bit is set to 1, the PPG output is masked with LOW output regardless of the cycle and duty 
set values. 
 
When  

OSEL in bit 3 is set to inverted output,  setting PMSK to 1
  masks the output with HIGH. 
 
Bit Description 
0 Normal output 
1 Fixed to LOW output 
 
[bit 9:8] EGS1, EGS0: Trigger input edge selection bits    These bits select a valid edge for  input waveforms as an external start cause and set the trigger condition. 
   When the initial value or 0b00 is set, the timer is not started by external waveforms because the setting 
means that no valid edge is selected for input waveforms. 
 
If the STRG 

bit is set to 1, software triggering  is enabled regardless 
 of the EGS1 and EGS0 settings. 
 
  Changes to EGS1 or EGS0 must be made when the counting is stopped (CTEN = 0). However, it is 
possibl

e to make changes at the same time you set 1 to the CTEN bit. 
Bit 9 Bit 8 Description 
0 0  Trigger input disabled 
0 1  Rising edge 
1 0 Falling edge 
1 1  Both edges 
 
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