Fujitsu Series 3 Manual
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2. CSIO (Clock Sync Serial Interface) interrupts 2. CSIO (Clock Sync Serial Interface) interrupts The CSIO interrupts contain the receive interrupt and the transmit interrupt. These interrupt requests can be generated if: - A receive data is set in the Receive Data Register (RDR) or a data receive error occurs. - A transmit data is transferred from the Transmit Data Register (TDR) to the transmit shift register and the data transmission is started - The transmit bus is idle (No data transmission occurs). - A transmit FIFO data is requested. CSIO interrupts Ta b l e 2 - 1 shows the CSIO interrupt control bits and the interrupt causes. Table 2-1 CSIO interrupt control bits and interrupt causes Interrupt type Interrupt request flag bit Flag register Interrupt cause Interrupt cause enable bit Operation to clear interrupt request flag A single-byte reception Reading from the received data register (RDR) Reception of a data volume matching the value set for FBYTE. RDRF SSR The FRIIE bit is 1, receive FIFO contains valid data, and the Receive Idle state continues more than 8 hours. Reading from the Received Data Register (RDR) until receive FIFO is emptied Reception ORE SSR Overrun error SCR:RIE Setting the Receive Error Flag Clear bit (SSR:REC) to 1 TDRE SSR The Transmit Data Register is empty. SCR:TIE Writing to the Transmit Data Register (TDR) or setting the transmit FIFO operation enable bit to 1 when the transmit FIFO operation enable bit is set to 0 and valid data are present in transmit FIFO (re-transmitting data) *1 TBI SSR No data transmission SCR:TBIE Writing to the Transmit Data Register (TDR) or setting the transmit FIFO operation enable bit to 1 when the transmit FIFO operation enable bit is set to 0 and valid data are present in transmit FIFO (re-transmitting data) *1 Transmission FDRQ FCR1 Transmit FIFO is empty. FCR1:FTIE The FIFO transmit data request bit (FCR1:FDRQ) is set to 0 or transmit FIFO is full. *1 Set the TIE bit to 1 only after the TDRE bit has been set to 0. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 855 MB9Axxx/MB9Bxxx Series
2. CSIO (Clock Sync Serial Interface) interrupts 2.1. Receive interrupt and flag set timing Data reception can be interrupted by a Receive Completion (SSR:RDRF) or a Receive Error Occurrence (SSR:ORE). Receive interrupt and flag set timing When the last data bit is detected, the received data is stored in the Receive Data Register (RDR). When the data reception is completed (SSR:RDRF=1) or when a data receive error occurs (SSR:ORE=1), each flag is set. If a receive interrupt is enabled (SSR:RIE =1) during this time, a receive interrupt occurs. If a recei ve e rror occurs, data in the Receive Data Register (RDR) is invalidated. Figure 2-1 Data receiving and flag set timing SCK SIN Receive data sampling D0 D1 D2 D3 D4 D5 D6 D7 RDRF A receive interrupt occurred.Note: This figure shows the signal timing under the following conditions. SCR: MS=1, SPI=0 ESCR: L2 to L0=0b000 SMR:SCINV=0, BDS=0, SCKE=0, SOE=0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 856 MB9Axxx/MB9Bxxx Series
2. CSIO (Clock Sync Serial Interface) interrupts Figure 2-2 ORE (Overrun Error) flag set timing SCK SIN Receive data sampling D0 RDRF An overrun error occurred. ORE Note: This figure shows the signal timing under the following conditions. SCR: MS=1, SPI=0 ESCR: L2 to L0=0b000 SMR:SCINV=0, BDS=0, SCKE=0, SOE=0 Precautions: If the next data is transferred be fore the receive data is read (RDRF=1), an overrun error occurs. D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 857 MB9Axxx/MB9Bxxx Series
2. CSIO (Clock Sync Serial Interface) interrupts 2.2. Interrupt occurrence and flag set timing when receive FIFO is used If receive FIFO is used, an interrupt occurs when the FBYTE data (preset for the FBYTE register (FBYTE)) is received. Receive interrupt and flag set ti ming when receive FIFO is used If receive FIFO is used, an interrupt occurs de pending on the value set for the FBYTE register. When full FBYTE data is received, the receive data full flag (SSR:RDRF) of the Serial Status Register is set to 1. If a receive interrupt (SCR:RIE) is enabled during this time, a receive interrupt occurs. If all of the following conditions are satisfied and if th e receive idle state continues for more than 8 baud rate clocks, the interrupt flag (RDRF) is set to 1. The receive FIFO idle detect enable bit (FRIIE) is 1. The number of data sets stored in the recei ve FIFO does not reach the transfer count. If the RDR data is read during counting of 8 clocks, this counter is reset to 0, and counting for 8 clocks is restarted. If receive FIFO is disabled, this counter is reset to 0.If data remains in the receive FIFO and if receive FIFO is enabled, the data counting is restarted. When the Receive Data Register (RDR) data is all read and receive FIFO is emptied, the receive data full flag (SSR:RDRF) is cleared. If the valid receive data amount is the same as the FI FO capacity and if the next data is received, an overrun error (SSR:ORE=1) occurs. Figure 2-3 Receive interrupt occurrence timing when receive FIFO is used Receive data FIFOBYTE (Receive) RDRF 1st byte 3 An interrupt occurs when the FBYTE (transmit data) count matches the receive data count. Data reading from RDRAll receive data are read. SCK Valid byte display 0123210 1 2 3210 1 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 6th byte FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 858 MB9Axxx/MB9Bxxx Series
2. CSIO (Clock Sync Serial Interface) interrupts Figure 2-4 ORE (Overrun Error) flag bit set timing Receive data FIFOBYTE (Receive) RDRF 1st byte 60 An interrupt occurs when the FIFOBYTE (receive data) count +1 matches the receive data count. An overrun error occurred. SCK Valid byte display59 ORE Auxiliary notes: If the FIFO buffer capacity is displayed by the FIFOBYTE and if the next data is received, an overrun error occurs. This figure shows a case where a 64-byte FIFO capacity is applied. 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 60 61 62 63 64 FUJITSU SEMICON DUCT OR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 859 MB9Axxx/MB9Bxxx Series
2. CSIO (Clock Sync Serial Interface) interrupts 2.3. Transmit interrupt occurrence and flag set timing A transmit interrupt occurs if data is transferred from the Transmit Data Register (TDR) to the transmit shift register (SSR:TDRE=1) and it is transmitted, or if no data is transmitted (SSR:TBI=1). Transmit interrupt occurrence and flag set timing Transmit data empty flag (SSR:TDRE) set timing After data has been transferred from the Transmit Data Register (TDR) to the transmit shift register, the next data can be written in the TDR (SSR:TDRE=1). If a transmit interrupt is enabled (SCR:TIE=1) during this time, a transmit interrupt occurs. As the SSR:TDRE bit is read only, the SSR:TDRE bit is cleared to 0 when data is written to the Transmit Data Register (TDR). Figure 2-5 Transmit data empty flag (SSR:TDRE) set timing SCK Transmit data TDRE Data writing in TDR D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 A transmit interrupt occurred. Transmit bus idle flag (SSR:TBI) set timing If the Transmit Data Register is empty (SSR:TDRE=1) an d no data is transmitted, the SSR:TBI bit is set to 1. If a transmit bus idle interrupt is enabled (SCR: TBIE=1) during this time, a transmit interrupt occurs. When transmit data is written to the Transmit Data Register (TDR), both the SSR:TBI bit and the transmit interrupt request are cleared. Figure 2-6 Transmit bus idle flag (TBI) set timing SCK Transmit data TBI Data writing in TDR D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 A transmit interrupt occurred due to a Bus Idle state. D5 TDRE FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 860 MB9Axxx/MB9Bxxx Series
2. CSIO (Clock Sync Serial Interface) interrupts 2.4. Interrupt occurrence and flag set timing when transmit FIFO is used When transmit FIFO is used, an interrupt occurs if the buffer contains no data. Transmit interrupt occurrence and flag se t timing when transmit FIFO is used If transmit FIFO contains no data , the FIFO transmit data request bit (FCR1:FDRQ) is set to 1. If a FIFO transmit interrupt is enabled (FCR1:FTIE=1), a transmit interrupt occurs. If you have written the required data in transmit FIFO after occurrence of a transmit interrupt, clear the interrupt request by setting the FIFO transmit data request bit (FCR1:FDRQ) to 0. When transmit FIFO is filled with data, the FIFO transmit data request bit (FCR1:FDRQ) is set to 0. You can check a presence of data in transmit FI FO by reading the FIFO Byte Register (FBYTE). If FBYTE=0x00, no data exists in transmit FIFO. Figure 2-7 Transmit interrupt occurrence timing when transmit FIFO is used Transmit data FIFOBYTE display FDRQ Data writing in Transmit FIFO buffer TDRE SCK 0 TXE 1st byte Cleared if set to 0. A transmit interrupt occurred. (*1) *1: The FDRQ bit is set to 1 as the Transmit FIFO buffer is empty. *2: The TDRE bit is set to 1 as the Transmit Buffer register contains no data. The Transmit buffer is empty. (*2) 2nd byte 3rd byte 4th byte 12 1 0 1 0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 861 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations 3. CSIO (Clock Sync Serial Interface) operations The clock synchronous data transmission is used. 3.1. Normal transfer (I) Features Item Description 1 Serial clock (SCK) signal detect level HIGH 2 Transmit data output timing SCK signal falling edge 3 Receive data sampling SCK signal rising edge 4 Data length 5 to 9 bits Register settings The register values required for normal data transfer (I) are listed on the table below. Table 3-1 Normal transfer (I) register settings Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 09Bit 08 Bit 07Bit 06 Bit 05Bit 04Bit 03 Bit 02 Bit 01Bit 00 UPCL MS SPIRIE TIE TBIE RXETXEMD2 MD1 MD0WUCR SCINV BDS SCKE SOESCR/ SMR 0 1/0 0 * * * * * 0 1 0 0 0 * 1/0 * REC - - - ORE RDRF TDRE TBISOP - - WT1 WT0 L2 L1 L0SSR/ ESCR 0 - - - - - - - 0 - - * * * * * D8D7D6 D5D4D3 D2 D1 D0TDR/ RDR * * * * * * * * * - B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0BGR1/ BGR 0 - * * * * * * * * * * * * * * * 1 : Set to 1. 0 : Set to 0. * : User-dependent values The ab ove bit setting (1/0) varies depending on the master or slave mode operation. Set as follows. During m a ster mode operation: SCR:MS=0, SMR:SCKE=1 During slave mode operation: SCR:MS=1, SMR:SCKE=0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 862 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Normal transfer (I) timing chart * A D7 Data transmission SCK SOUT TDR RW TXE D0D 7 D1 D2 D3 D4 D5 D6 Data reception SIN RXE Sampling 1st byte RDRF TDRE D0D1 D2D3 D4 D 5 D6 2nd byte RDR RD D7 D0 D7 D1 D2 D3D4D5D6 D0D1 D2D3 D 4 D5 D6 D7 value if SCR:MS=1 HIGH if SCR:MS=0 : * A FUJITSU SEMICONDUCT OR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 863 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Master mode operation (SCR:MS=0, SMR:SCKE=1) Data transmission 1. If serial data output is enabled (SMR:SOE=1), da ta transmission is enabled (SCR:TXE=1) and data reception is disabled (SCR:RXE=0), and when the transmit data is written in the TDR, the SSR:TDRE bit is set to 0. This causes the transmit data to be output in synchronization with a falling edge of the serial clock (SCK) output. 2. When the transmit data of the first bit is output, the SSR:TDRE bit is set to 1. Therefore, if the transmit interrupt is enabled (SCR:TI E=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. Data reception 1. If the serial data output is disabled (SMR:SOE=0), data transmission is enabled (SCR:TXE=1) and data reception is enabled (SCR:RXE=1), and when a dummy da ta is written in the TDR, the receive data is sampled at a rising edge of serial clock (SCK) output. 2. When the last bit is received, th e SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1) during this time, a r eceive interrupt request is output. The receive data (RDR) can be read during this time. 3. When the receive data (RDR) is read, the SSR:RDRF bit is cleared to 0. To perform data reception only, write a dummy data in the TDR so t hat the serial clock (SCK) is output. If the FIFO transmission and reception are enabled, th e serial clocks (SCK) for the preset number of frames are output when the transmit fra mes are set in the FBYTE register. Data transmission and reception 1. To perform data transmission and reception simultaneously, enable the serial data output (SMR:SOE=1) and enable the data transmission and reception (SCR:TXE, RXE=1). 2. When the transmit data is written in the TDR, the SSR:TDRE bit is set to 0 and the transmit data is output in synchronization with a falling edge of the serial clock (SCK) output. When the transmit data of the first bit is output, the SSR:TDRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. 3. The receive data is sampled at a rising edge of the serial clock (SCK) output. When the last bit of receive data is received, the SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive da ta (RDR) can be read during this time. When the receive data is read, the SSR:R DRF bit is cleared to 0. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 864 MB9Axxx/MB9Bxxx Series