Fujitsu Series 3 Manual

							 
4. Registers of Multifunction Timer 
 
[bit3:2] Reserved 
Process Function 
Write 0 must be written at write access. 
Read 0 is read. 
 
[bit4] WFIR.TMIF10 
Process Value  Function 
  Write - Writing is ignored. 
0  Indicates that WFG10 timer interrupt has not been generated. Read 
1 Indicates that WFG10 timer interrupt has been generated. 
 
[bit5] WFIR.TMIC10 
Process Value  Function 
0 Does nothing. Write 
1 Clears WFIR.TMIF10 and deasserts  the WFG10 timer interrupt signal. 
Read - 0 is always read. 
 
[bit6] WFIR.TMIE10 
Process Value  Function 
0 Does nothing. Write 
1 Starts the WFG10 timer (or does nothing, if it has already been started). 
0 Indicates that the WFG10 tim er is currently stopped. Read 
1 Indicates that the  WFG10 timer is currently in operation. 
 
[bit7] WFIR.TMIS10 
Process Value  Function 
0 Does nothing. 
Write 
1 Stops the WFG10 timer (and also clears an interrupt at the same time, if it 
occurs, and deasserts the interrupt signal). 
Read 
- 0 is always read. 
 
WFIR.TMIF10 is a register that check s the state of WFG10 timer interrupt. 
WFIR.TMIC10 is a register that  clears WFG10 timer interrupt and  deasserts the interrupt signal. 
WFIR.TMIE10 is a register th at starts the WFG10 timer. 
WFIR.TMIS10 is a register that stops the WFG10 time r, clears the interrupt and deasserts the interrupt 
signal. 
If the WFG timer for ch.10 of WFG is not used for waveform generation (WFSA10.TMD[2:0]=000, 001), 
the WFG10 timer can be used as an independent reload timer which generates interrupts regularly to CPU. 
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4. Registers of Multifunction Timer 
 
Figure 4-8 shows a diagram of the operation when the WFG timer is used as a reload timer. 
Figure 4-8 Diagram of Operation when WFG Timer is Used as Reload Timer 
 
CPU operation
WFG timer count
  0N
WFG timer interrupt1
Start
2
Clear
N-1N-2・・・
WFTM reg.
N
N12N-1N-2NN-1
Stop
・・・  0
Load initial 
count value・・・
  
 
Below is the procedure for using the WFG timer as a reload timer. 
  First, set the initial value of the timer to the WFTM  register and the clock division ratio to WFSA.DCK. 
   Interval time of the interrupt generated from the timer = (WFTM value  Clearing the  timer interrupt > Starting the timer (Lowest priority) 
 
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4. Registers of Multifunction Timer 
 
[bit8] WFIR.TMIF32 
Process Value Function 
Write - Writing is ignored. 
0  Indicates that WFG32 timer interrupt has not been generated. Read 
1 Indicates that WFG32 timer interrupt has been generated. 
 
[bit9] WFIR.TMIC32 
Process Value  Function 
0 Does nothing. Write  
1 Clears WFIR.TMIF32 and deasserts the  interrupt signal of the WFG32 timer.
Read - 0 is always read. 
 
[bit10] WFIR.TMIE32 
Process Value  Function 
0 Does nothing. Write 
1 Starts the WFG32 timer (or does nothing, if it has already been started). 
0 Indicates that the WFG32 tim er is currently stopped. Read 
1 Indicates that the  WFG32 timer is currently in operation. 
 
[bit11] WFIR.TMIS32 
Process Value  Function 
0 Does nothing. 
Write  
1 Stops the WFG32 timer (and also clears an interrupt at the same time, if it 
occurs, and deasserts the interrupt signal).   
Read 
- 0 is always read. 
 
WFIR.TMIF32 is a register that check s the state of WFG32 timer interrupt. 
WFIR.TMIC32 is a register that  clears WFG32 timer interrupt and  deasserts the interrupt signal. 
WFIR.TMIE32 is a register th at starts the WFG32 timer. 
WFIR.TMIS32 is a register that stops the WFG32 time r, clears the interrupt and deasserts the interrupt 
signal. 
If the WFG timer for ch.32 of WFG is not used for waveform generation (WFSA32.TMD[2:0]=000, 001), 
the WFG32 timer can be used as an independent reload timer which generates interrupts regularly to CPU. 
This register is used in the same way as  for WFIR.TMIF10, WFIR.TMIC10, WFIR.TMIE10 and 
WFIR.TMIS10. 
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[bit12] WFIR.TMIF54 
Process Value Function 
Write - Writing is ignored. 
0  Indicates that the WFG54 timer interrupt has not been generated. Read 
1 Indicates that the WFG54 timer interrupt has been generated. 
 
[bit13] WFIR.TMIC54 
Process Value  Function 
0 Does nothing. Write 
1 Clears WFIR.TMIF54 and deasserts the  interrupt signal of the WFG54 timer.
Read - 0 is always read. 
 
[bit14] WFIR.TMIE54 
Process Value  Function 
0 Does nothing. Write 
1 Starts the WFG54 timer (or does nothing, if it has already been started). 
0 Indicates that the WFG54 tim er is currently stopped. Read 
1 Indicates that the  WFG54 timer is currently in operation. 
 
[bit15] WFIR.TMIS54 
Process Value  Function 
0 Does nothing. 
Write 
1 Stops the WFG54 timer (and also clears an interrupt at the same time, if it 
occurs, and deasserts the interrupt signal). 
Read 
- 0 is always read. 
 
WFIR.TMIF54 is a register that check s the state of WFG54 timer interrupt. 
WFIR.TMIC54 is a register that  clears WFG54 timer interrupt and  deasserts the interrupt signal. 
WFIR.TMIE54 is a register th at starts the WFG54 timer.   
WFIR.TMIS54 is a register that stops the WFG54 time r, clears the interrupt and deasserts the interrupt 
signal. 
If the WFG timer for ch.54 of WFG is not used for waveform generation (WFSA54.TMD[2:0]=000, 001), 
the WFG54 timer can be used as an independent reload timer which generates interrupts regularly to CPU. 
This register is used in the same way as  for WFIR.TMIF10, WFIR.TMIC10, WFIR.TMIE10 and 
WFIR.TMIS10. 
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4. Registers of Multifunction Timer 
 
4.3.14.  ICU Connecting FRT Select Register (ICFS) 
ICFS is an 8-bit register that selects and sets FRT to be connected to ICU. 
Each mounted channel has two registers: ICFS10 and ICFS32. 
ICFS10 controls ICU ch1 and ICU ch0. 
ICFS32 controls ICU ch3 and ICU ch2. 
ICFS10 is located at an even-numbered address, while ICFS32 is located at an 
odd-numbered address; therefore, their bit positions are [7:0] and [15:8]. 
 Configuration of Register 
Bit  15/7 14/6 13/5  12/4 11/3 10/2  9/1 8/0 
Field FSI1[3:0]  FSI0[3:0] 
Attribute R/W  R/W 
Initial Value 0 0 0  0 0 0 0 0 
 Functions of Register 
[bit3:0/11:8] ICFS.FSI0[3:0] 
Process Value  Function 
0000 Connects FRT ch.0 to ICU ch.(0). 
0001 Connects FRT ch.1 to ICU ch.(0). 
0010 Connects FRT ch.2 to ICU ch.(0). 
0011 
0100  For models with multiple MFT units: Connects FRT of an external MFT.     
For models with one MFT unit: Setting prohibited Write 
Other than 
above  Setting prohibited 
Read 
- Reads the register setting. 
 
[bit7:4/15:12] ICFS.FSI1[3:0] 
Process Value  Function 
0000 Connects FRT ch.0 to ICU ch.(1). 
0001 Connects FRT ch.1 to ICU ch.(1). 
0010 Connects FRT ch.2 to ICU ch.(1). 
0011 
0100  For models with multiple MFT units: Connects FRT of an external MFT. 
For models with one MFT unit: Setting prohibited Write 
Other than 
above  Setting prohibited 
Read 
- Reads the register setting. 
 
ICFS.FSI0[3:0] is a register that selects FRT to be connected to ICU-ch.(0) for use. 
ICFS.FSI1[3:0] is a register that selects FRT to be connected to ICU-ch.(1) for use. 
For models with multiple MFT units, the connection to FRT that exists in another MFT unit can be selected. 
For related settings, see  5.1 Connection of Model Containing Multiple MFT’s . 
C hange th
e set

ting of these regist ers, while the operation of the IC U to be connected is disabled. 
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4. Registers of Multifunction Timer 
 
4.3.15.  ICU Control Register A (ICSA) 
ICSA is an 8-bit register that controls ICU’s operation. 
Each mounted channel has two registers: ICSA10 and ICSA32. 
ICSA10 controls ICU ch1 and ICU ch0. 
ICSA32 controls ICU ch3 and ICU ch2. 
 Configuration of Register 
 
Bit 7 6 5 4 3 2 1 0 
Field ICP1 ICP0 ICE1 ICE0 EG1[1:0] EG0[1:0] 
Attribute  R/W R/W R/W  R/W R/W  R/W 
Initial Value 0 0 0  0 0 0 0 0 
 
  Functions of Register 
[bit1:0] ICSA.EG0[1:0] 
Process Value  Function 
00 Disables the operation of ICU ch.(0). 
Ignores IC(0) signal input. 
01 Enables the operation of ICU ch.(0). 
Treats only the rising edge of IC(0) signal input as a valid edge. 
10 Enables the operation of ICU ch.(0). 
Treats only the falling edge of IC(0) signal input as a valid edge. 
Write 
11 Enables the operation of ICU ch.(0). 
Treats both the rising and falling edges of IC(0) signal input as valid edges. 
Read 
- Reads the register setting. 
 
[bit3:2] ICSA.EG1[1:0] 
Process Value  Function 
00 Disables the operation of ICU ch.(1). 
Ignores IC(1) signal input. 
01 Enables the operation of ICU ch.(1). 
Treats only the rising edge of IC(1) signal input as a valid edge. 
10 Enables the operation of ICU ch.(1). 
Treats only the falling edge of IC(1) signal input as a valid edge. 
Write 
11 Enables the operation of ICU ch.(1). 
Treats both the rising and falling edges of IC(1) signal input as valid edges. 
Read 
- Reads the register setting. 
 
ICSA.EG0[1:0] is a register that en ables/disables the operation of ICU-ch.(0) and selects a valid edge(s). 
ICSA.EG1[1:0] is a register that en ables/disables the operation of ICU-ch.(1) and selects a valid edge(s). 
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If a valid edge is detected at the input signal when ICU’s operation is enabled, it performs the capture 
operation that captures FRT’s count output to the ICCP register. At the same time, it notifies CPU that the 
valid edge has been detected. The valid edge of the input signal can be selected from the rising edge only, 
the falling edge only, or both rising and falling edges. 
When the operation is disabled, it does nothing and ignores the input signal. 
Figure 4-9  shows an example of ICU’s operation. 
IC U-ch.0 i
n

dicates the operation to be performed upon detection of the rising edge of IC0 signal input. 
ICU-ch.1 indicates the operation to be performed upon detection of the falling edge of IC1 signal input. 
ICU-ch.2 indicates the operation to be performed upon detection of both the rising and falling edges of IC 
signal input. 
Figure 4-9 Example of ICU’s Operation 
 
ICU behavior
FRT count
0x0000
0xFFFF
time
ICCP0 reg.
0xBFFF 0x7FFF0x3FFF
IC0 input
ICCP1 reg. IC1 input
ICCP2 reg. IC2 input
0x7FFF0x3FFF
0xBFFF0x7FFF
0x3FFF0x7FFF
 
 
[bit4] ICSA.ICE0 
Process Value  Function 
0 Does not generate interrupt, when 1 is set to ICSA.ICP0. Write 
1 Generates interrupt, when 1 is set to ICSA.ICP0. 
Read - Reads the register setting. 
 
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4. Registers of Multifunction Timer 
 
[bit5] ICSA.ICE1 
Process Value Function 
0 Does not generate interrupt, when 1 is set to ICSA.ICP1. Write 
1 Generates interrupt, when 1 is set to ICSA.ICP1. 
Read - Reads the register setting 
 
ICSA.ICE0 is a register that specifies whether to notify  CPU of the event that 1 is set to ICSA.ICP0 as an 
interrupt (enabling interrupt) or not to notify it (disabling interrupt). 
ICSA.ICE1 is a register that specifies whether to notify  CPU of the event that 1 is set to ICSA.ICP1 as an 
interrupt (enabling interrupt) or not to notify it (disabling interrupt). 
See  5.2 Treatment of Event Detect Register and Interrupt . 
[bit6] ICSA.IC P0 
Process Value 
Function 
0 Clears this register to 0. Write 
1 Does nothing. 
0 Indicates that no valid edge has been 
detected at ICU ch.(0) and no capture 
operation has been performed. 
Read 
1 Indicates that a valid edge has been de
tected at ICU ch.(0) and the capture 
operation has been performed. 
Read at RMW access  1 is always read. 
 
[bit7] ICSA.ICP1 
Process Value  Function 
0 Clears this register to 0. Write 
1 Does nothing. 
0 Indicates that no valid edge has been 
detected at ICU ch.(1) and no capture 
operation has been performed. 
Read 
1 Indicates that a valid edge has been de
tected at ICU ch.(1) and the capture 
operation has been performed. 
Read at RMW access  1 is always read. 
 
ICSA.ICP0 is a register to which 1 is set upon det ection/capture of a valid edge, when the operation of 
ICU-ch.(0) is enabled. 
ICSA.ICP1 is a register to which 1 is set upon det ection/capture of a valid edge, when the operation of 
ICU-ch.(1) is enabled. 
By reading from this register, it can be determined whether or not a valid edge has been detected and the 
capture operation has been performed. 
This register can be cleared by writing 0. 
This register does nothing, if 1 is written. Always  write 1 to the register when rewriting to another 
register in the same address area. 
1 is always read from this register at RMW access. 
See  5.2 Treatment of Event Detect Register and Interrupt . 
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4. Registers of Multifunction Timer 
 
4.3.16.  ICU Control Register B (ICSB) 
ICSB is an 8-bit register that reads the operation state of ICU. 
Each mounted channel has two registers: ICSB10 and ICSB32. 
ICSB10 reads the operation state of ICU ch1 and ICU ch0. 
ICSB32 reads the operation state of ICU ch3 and ICU ch2. 
 Configuration of Register 
Bit  15 14 13  12 11 10  9 8 
Field  Reserved Reserved Reserved ReservedReservedReserved  IEI1 IE10 
Attribute  - - -  - - - R R 
Initial Value  - - -  - - - 0 0 
 
  Functions of Register 
[bit8] ICSB.IEI0 
Process Value  Function 
Write - Writing is ignored. 
0  Indicates that the latest capture operation of ICU ch.(0) was performed at a 
falling edge. 
Read 
1 Indicates that the latest capture operation of ICU ch.(0) was performed at a rising 
edge. 
 
[bit9] ICSB.IEI1 
Process Value  Function 
Write - Writing is ignored. 
0  Indicates that the latest capture operation of ICU ch.(1) was performed at a 
falling edge. 
Read 
1 Indicates that the latest capture operation of ICU ch.(1) was performed at a rising 
edge. 
 
ICSB.IEI0 is a register th at indicates the latest valid edge of ICU-ch.(0). 
ICSB.IEI1 is a register th at indicates the latest valid edge of ICU-ch.(1). 
By reading from this register, at which edge the latest capture operation was performed can be determined. 
As the initial value of this register is 0, 0 can be  read if the capture operation has never been performed. 
It is also updated every time the valid edge of an  input signal is detected. After the capture operation is 
performed, it is necessary to read from this register before the next valid edge. 
[bit15:10] Reserved 
Process Function 
Write  The written value is ignored. 
Read An undefined value is read. 
 
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4. Registers of Multifunction Timer 
 
4.3.17.  ICU Capture value store register (ICCP) 
ICCP is a 16-bit register that reads the value captured to ICU. 
Each mounted channel has four registers: ICCP0, ICCP1, ICCP2 and ICCP3. 
ICCP0 stores the capture value of ICU ch0. 
ICCP1 stores the capture value of ICU ch1. 
ICCP2 stores the capture value of ICU ch2. 
ICCP3 stores the capture value of ICU ch3. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
 
Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field ICCP[15:0] 
Attribute R 
Initial  Va l u e   X X X X X X X X X X X X X X X X 
 
  Functions of Register 
[bit15:0] ICCP.ICCP[15:0] 
Process Function 
Write  Writing is ignored. 
Read Reads the data captured to ICU. 
 
ICCP is a 16-bit register that reads th e value captured at each channel of ICU. 
As the initial value of this register is undefined, a m eaningless value is read if the capture operation has 
never been performed. 
This register is updated every time the valid edge of  an input signal is detected. After the capture operation 
is performed, it is necessary to read from th is register before the next valid edge. 
 
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