Fujitsu Series 3 Manual

							 
4. CAN Registers 
 
[bit 4] RxOk: Successful message reception bit 
Bit Function 
0 No message has been transferred successfully on the CAN bus, or the bus is in 
idle state.    [Initial value] 
1 
A messages has been transferred successfully on the CAN bus. 
 
[bit 3] TxOk: Successful message transmission bit 
Bit Function 
0  The bus is in idle state, or no message has been sent successfully.    [Initial value] 
1  A messages has been sent successfully. 
 
 
The R x

Ok and TxOk bits can be reset only by the CPU. 
 [bit 2:0] LEC: Last error code bits 
Bit 2:0  State  Function 
0 Normal Successful transmission or reception. 
[Initial value] 
1 Stuff error Six or more dominant or recessive bits have been detected 
consecutively in a message. 
2 
Form error  A wrong fixed format part  of a received frame has been detected. 
3 Ack error  A sent message was not acknowledged by another node. 
4 Bit 1 error  In the sent message data excluding the arbitration field, bits that have 
been sent as recessive data is detected as dominant data. 
5 
Bit 0 error  In the sent message data excluding the arbitration field, bits that have 
been sent as dominant data is detected as recessive data. 
This bit is set each time 11 recessive bits are detected during bus 
recovery. The bus recovery sequence can be monitored by reading 
this bit. 
6 CRC error 
The CRC data in a received message did not match with the 
calculated CRC value. 
7 Undetected If the CPU wrote 7 to the LEC bit, and the LEC value is read as 7 
afterward, it indicates that no bus 
event has been detected since the 
CPU wrote the value. (The bus is in idle state) 
  The LEC bit holds a code that indicates the last erro r occurred on the CAN bus. When a message has been 
transferred (sent or received) without error, this bit is cleared to 0. The undetected code 7 is written by 
the CPU to check for code updates. 
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   If the BOff and EWarn bits change while the EIE bit is  1, or if th
 e RxOk, TxOk, and LEC bits change 
while the SIE bit is 1, the status interrupt code  (0x8000) is written to the CAN Interrupt Register. 
   Writing from the CPU updates the RxOk and TxOk bits, and this erases the RxOk and TxOk bits set by 
the CAN controller. If the RxOk and TxOk bits are used, clear the RxOk and TxOk bits within the time 
(45 x BT) after they are set to 1. BT indicates one bit time. 
   If a change of the LEC bit causes an interrupt while  the SIE bit is 1, do not write to the CAN Status 
Register. 
   No interrupt is caused by a change of the EPass bit,  or writing to the RxOk, TxOk, and LEC bits from the 
CPU. 
   When the BOff bit has turned to 1, the EPass bit  and EWarn bit are 1. When the EPass bit has turned 
to 1, the EWarn bit is 1. 
   The status interrupt (0x8000) of the CAN Interrupt Register is cleared by  reading this register. 
 
 
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4.2.3. CAN Error Counter (ERRCNT) 
The CAN Error Counter indicates the receive error passive, the receive error counter, and the 
send error counter. 
 Register configuration 
- CAN Error Counter (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field RP REC6-0 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Error Counter (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field TEC7-0 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0 0 0 0 0 
 
  Register functions 
[bit 15] RP: Receive error passive indication 
Bit Function 
0  The receive error counter is below the error passive level. 
[Initial value] 
1 The receive error counter has reached the 
error passive level defined in the CAN 
specification. 
 
[bit 14:8] REC6-0: Receive error counter  A receive error counter value. The range of the  receive error counter value is between 0 and 127. 
If the receive error counter reaches or exceeds 128, the RP  bit is set to 1, and the counter is not refreshed. 
Example:  If a receive error adds 8  to REC6-0 = 127 with RP = 0,   
      then REC6-0 = 127 with RP = 1. 
  If a receive error adds 8 to  REC6-0 = 126 with RP = 0,   
      then REC6-0 = 126 with RP = 1.   
  If a receive error adds 8 to REC6-0 = 119 with RP = 0,   
      then REC6-0 = 127 with RP = 0. 
  If reception is successful when  REC6-0 = 126 and RP = 1,   
      then REC6-0 = 125 and RP = 0. 
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[bit 7:0] TEC7-0: Send error counter A send error counter value. The range of the send error counter value is between 0 and 255. 
If the send error counter reaches or  exceeds 256, the Init bit of the CAN Control Register is set to 1, and 
the counter is not refreshed. 
Example:  If a send error adds 8 to TEC7-0 = 255 with Init = 0,   
    then TEC7-0 = 255 with Init = 1. 
  If a send error adds 8 to TEC7-0 = 254 with Init = 0,   
    then TEC7-0 = 254 with Init = 1.   
  If a receive error adds 8 to  TEC7-0 = 247 with Init = 0,   
    then TEC7-0 = 255 with Init = 0. 
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4.2.4. CAN Bit Timing Register (BTR) 
The CAN Bit Timing Register configures the prescaler and the bit timing. 
 Register configuration 
- CAN Bit Timing Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedTSeg2 TSeg1 
Attribute  R0,W0 R/W R/W  R/W R/W R/W  R/W R/W 
Initial value 0 0 1  0 0 0 1 1 
 
- CAN Bit Timing Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field SJW  BRP 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 1 
 
  Register functions 
[bit 15] Reserved bit 
Reserved bits are read as 0, an d must be set to 0 when writing. 
[bit 14:12] TSeg2: Time segment 2 setting bits  Valid programmed values are 0 to 7. The TSeg2 + 1 value is the time segment 2. 
The time segment 2 is equivalent to the Phase Buffer Segment (PHASE_SEG2)  in the CAN specification. 
[bit 11:8] TSeg1: Time segment 1 setting bits  Valid programmed values are 1 to 15. The 0 value must not be used. The TSeg1 + 1 value is the time 
segment 1. 
The time segment 1 is equivalent to the Propaga tion Segment (PROP_SEG) + Phase Buffer Segment 1 
(PHASE_SEG1) in the CAN specification. 
[bit 7:6] SJW: Resynchronization jump width setting bits  Valid programmed values are 0 to 3. The SJW + 1 value is the resynchronization jump width. 
[bit 5:0] BRP: Baud rate prescaler setting bits  Valid programmed values are 0 to 63. The BRP + 1 value is the baud rate prescaler. 
It determines the basic unit of time quantum (tq) for the CAN controller by dividing the system clock (fsys). 
 
 
The C A

N Bit Timing Register and CAN Prescaler Extension Register must be configured while the Init bit 
and CCE bit in the C A

N Control Register are set to 1. 
 
 
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4.2.5. CAN Interrupt Register (INTR) 
The CAN Interrupt Register indicates message interrupt code and status interrupt code. 
 Register configuration 
- CAN Interrupt Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field IntId15-8 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Interrupt Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field IntId7-0 
Attribute  R,WX R,WX R,WX  R,WX R,WX R,WX  R,WX R,WX 
Initial value 0 0 0  0 0 0 0 0 
 
  Register functions 
Bit 15:0  Function 
0x0000 No interrupt 
0x0001 - 0x0020 An interrupt cause indicates a message object number. 
(Message interrupt code) 
0x0021 - 0x7FFF 
Unused. 
0x8000 Indicates an interrupt by a cha
nge in the CAN Status Register. 
(Status interrupt code) 
0x8001 - 0xFFFF  Unused. 
 
If two or more interrupts are pending, the CAN Interrupt Register indicates a high-priority interrupt code. If 
a high-priority interrupt code is generated while an in terrupt code is set to the CAN Interrupt Register, the 
CAN Interrupt Register is updated to the high-priority interrupt code. 
High-priority interrupt codes are arranged in the order of status interrupt code (0x8000), message interrupt 
codes (0x0001, 0x0002, 0x0003, ......, 0x0020). 
When the IE bit of the CAN Control Register is set to 1 while the IntId bit is not 0x0000, a CPU interrupt 
signal becomes active. When the IntId bit is set to 0x0000 (an interrupt cause is reset) or the IE bit of the 
CAN Control Register is reset to 0, an interrupt signal becomes inactive. 
To clear a message interrupt code, reset the In tPnd bit of the target message object (see 4.4 Message 
objects  for the message object) to 0. 
A  status interrupt code is cleared 
by readi

ng the CAN Status Register. 
 
  To rea

d the CAN Interrupt Register,  access it in halfword or word mode. 
 
 
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4.2.6. CAN Test Register (TESTR) 
The CAN Test Register is used to monitor the setting of test mode and RX pin. For\
 operations, 
see 3.7 Test mode. 
  Register configuration 
- CAN Test Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Test Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field Rx  Tx1 Tx0 LBack  Silent Basic Reserved  Reserved
Attribute  R,WX R/W R/W  R/W R/W R/W  R0,W0 R0,W0 
Initial value  r 0 0  0 0 0  0 0 
  The initial value r of Rx in bit 7 indicates the level on the CAN bus. 
 
  Register functions 
[bit 15:8] Reserved bits 
Reserved bits are read as 0, an d must be set to 0 when writing. 
[bit 7] Rx: Rx pin monitor bit 
Bit Function 
0  Indicates that the CAN bus is in the dominant state. 
1 Indicates that the CAN bus is in the recessive state. 
 
[bit 6:5] Tx1-0: TX pin control bit 
Bit 6  Bit 5 Function 
0 0 Normal operation.    [Initial value] 
0  1 Outputs a sampling point to the Tx pin. 
1  0 Outputs a dominant to the TX pin. 
1  1 Outputs a recessive to the TX pin. 
 
[bit 4] LBack: Loop back mode 
Bit Function 
0  Disables loop back mode.    [Initial value] 
1 Enables loop back mode. 
 
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[bit 3] Silent: Silent mode 
Bit Function 
0 Disables silent mode.    [Initial value] 
1 Enables silent mode. 
 
[bit 2] Basic: Basic mode 
Bit Function 
0  Disables basic mode. [Initial value] 
1 Enables basic mode. 
The IF1 register is used for a sent me
ssage, and the IF2 register for a received 
message. 
 
[bit 1:0] Reserved bits  Reserved bits are read as 0, an d must be set to 0 when writing. 
 
    After setting 1  to th

e Te
 st bit of the CAN Control Regi ster, write data to this register. When the Test bit 
of the CAN Control Register is set to 1, test mode becomes valid. If the Test bit of the CAN Control 
Register is set to 0 during processing, test mode changes to normal mode. 
   If the Tx bit is set to a value other than 00, no message can be sent. 
 
 
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4.2.7. CAN Prescaler Extension Register (BRPER) 
The CAN Prescaler Extension Register is used to extend the prescaler used in the CAN 
controller by combining it with the prescaler specified at a CAN bit timing. 
 Register configuration 
- CAN Prescaler Extension Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0 
 
- CAN Prescaler Extension Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field Reserved Reserved Reserved Reserved BRPE 
Attribute R0,W0 R0,W0 R0,W 0 R0,W0  R/W R/W  R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
  Register functions 
[bit 15:4] Reserved bits 
Reserved bits are read as 0, an d must be set to 0 when writing. 
[bit 3:0] BRPE: Baud rate prescaler extension bit  This bit is used to extend the baud rate prescaler up to 1023 by combining BRP and BRPE in the CAN Bit 
Timing Register. 
The value {BRPE (MSB: 4 bits), BRP (LSB: 6 bits)} + 1 is set as the prescaler value of the CAN 
controller. 
 
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4.3.  Message interface registers 
The CAN controller provides two message interface registers to control an access from the 
CPU to the message RAM. 
The CAN controller provides two message interface registers to control an access from the CPU to the 
message RAM. These two registers are used to avoi d a confliction between an access from the CPU to the 
message RAM and an access from the CAN controller to  the message RAM by buffering the data (message 
object) transferred or to be tran sferred. A message object (see  4.4 Message objects  for message object) is 
use d to collectively transfer data betwee
n t

h e message interface registers and message RAM. 
Two message interface registers have the same functions, excluding basic test mode, and can be operated 
independently. For example, the IF1 Message Interface Re gister can be used to write data to the message 
RAM while the IF2 Message Interface Register is be ing used to read data from the message RAM. Ta b l e  
4- 2
 shows two message interface registers. 
Each Messa ge 

Interface Regist er consists 

of two components: (1) Command Register (Command Request 
and Command Mask Registers) and (2 ) Message Buffer Register (Mask, Arbitration, Message Control, and 
Data Registers) controlled with the Command Regist er. The Command Mask Register indicates the data 
transfer direction and also which part in a message  object is to be transferred. The Command Request 
Register is used to select a message number an d perform the operation specified in the Command Mask 
Register. 
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