Fujitsu Series 3 Manual

							 
4. Registers of Multifunction Timer 
 
The table below shows examples of DCK[2:0] settings and the count clock cycle of the WFG timer. 
Count Clock Cycle of WFG Timer 
DCK[2:0] Clock 
Ratio  PCLK=25ns 
(40MHz)  PCLK=33.3ns 
(33MHz)  PCLK=50ns 
(25MHz) 
000  1  25ns 30ns 50ns 
001 2  50ns 61ns 100ns 
010 4  100ns 121ns 200ns 
011 8  200ns 242ns 400ns 
100 16  400ns 485ns 800ns 
101 32  800ns 970ns 
1.6s 
110 64  1.6μs 1.9 μs 
3.2s 
 
[bit5:3] WFSA.TMD[2:0] 
Process Value  Function 
000 Sets WFG’s operation mode to Through mode. 
001 Sets WFG’s operation mode to RT-PPG mode. 
010 Sets WFG’s operation mode to Timer- PPG mode. 
100  Sets WFG’s operation mode to RT dead timer mode. 
111 Sets WFG’s operation mode to PPG dead timer mode. 
Write 
Other than 
above  Setting prohibited 
Read 
- Reads the register setting. 
 
WFSA.TMD[2:0] is a register that selects WFG’s operation mode. 
For the operation modes by this register setting, see  4.5 Details of WFG Output Waveform . 
Whe n WFG
’

s operation mode is set to Through mode (TMD[2:0]=000) or RT-PPG mode (TMD[2:0]=001), 
the WFG timer can be used as an independent reload timer.   
Change the setting of this register while OCU and PPG timer unit to be connected are stopping. If the value 
set in this register is rewritten to a different value, the count state of the WFG timer is reset. 
[bit7:6] WFSA.GTEN[1:0] 
Process Value  Function 
00 Does not generate the CH_GATE signal. 
Write 
Other 
than 
above  Generates the CH_GATE signal. 
For details, see 
4.5 Details of WFG Output Waveform . 
Read - Reads the register setting. 
 
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4. Registers of Multifunction Timer 
 
WFSA.GTEN[1:0] is a register that selects the output condition of the CH_GATE for each channel of WFG, 
in combination with WFSA.TMD[2:0]. 
This register has no meaning, wh en WFSA.TMD[2:0] is set to 000,100,. Change the setting, while OCU 
and PPG timer units to be  connected are stopping. 
The CH_GATE signal is generated based on the RT  input signal and WFG timer operation at each channel 
of WFG (for details, see  4.5 Details of WFG Output Waveform ).  
The sta rt trigger sig
n

al (GATE signal) for the PPG ti mer unit is generated from the CH_GATE signal (for 
details, see the section regarding WFSA.PSEL[1:0]). 
The PPG timer unit to be connected to  WFG can start the output of the PPG signal, using the GATE signal, 
and each channel of WFG can superi mpose the PPG signal from the PPG timer unit on the RTO signal 
output (for details, see the section regarding WFSA.PGEN[1:0] and  4.5 Details of WFG Output 
Wa v e f o
r

m ). 
[bit9:8] WFSA.PSEL[1:0] 
Process Value  Function 
00 Sets the output destination of the GATE signal to ch.0 of the PPG timer unit.
Sets the input source of the PPG signal to ch.0 of the PPG timer unit. 
01 Sets the output destination of the GATE signal to ch.2 of the PPG timer unit.
Sets the input source of the PPG signal to ch.2 of the PPG timer unit. 
10 Sets the output destination of the GATE signal to ch.4 of the PPG timer unit.
Sets the input source of the PPG signal to ch.4 of the PPG timer unit. 
Write 
11 Setting prohibited 
Read  - Reads the register setting. 
 
WFSA.PSEL[1:0] is a register that  selects the PPG timer unit to be used at each channel of WFG. 
This register selects the PPG timer unit to be used as the output destination of the GATE signal and the 
input source of the PPG signal at once. Change the se tting of this register, while OCU and PPG timer unit to 
be connected are stopping.  Figure 4-6 shows a diagram of configuration of the PPG selector for MFTunit0. 
Figure 4-6 Diagram of Configuration of PPG Selector for MFTunit0 
 
SEL
SEL
SEL
PPG0
CH10_PPG
CH54_PPGSEL
SEL
SELCH54_GATE CH32_GATE
CH10_GATE
GATE0
CH32_PPG
WFSA10.PSEL[1:0]
WFSA32.PSEL[1:0]
WFSA54.PSEL[1:0]
WFG
ch.10
WFG 
ch.32
WFG 
ch.54
WFSA10.PSEL[1:0]
WFSA32.PSEL[1:0]
WFSA54.PSEL[1:0]           
PPG2
PPG4
GATE2
GATE4
 
 
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The following section describes the configuration and operation of the PPG selector. 
Each channel of WFG can output a trigger signal (CH_GATE signal) to start the PPG timer unit. 
The CH10_GATE signal, CH32_GATE signal and CH54_GATE signal refer to the GATE signal for each 
channel of WFG, which has been generated at WFG ch10, WFG ch32 and WFG ch54, respectively. 
After its output is selected by WFSA.PSEL[1:0] for each PPG timer unit to be connected, each CH_GATE 
signal undergoes logic OR by PPG timer  unit and is output to each PPG unit. 
The GATE0signal, GATE2 signal and GATE4 signal refer to the GATE signal that is output to ch.0, ch.2 
and ch.4 of the PPG timer unit, respectively. 
Each PPG timer unit can be started by the GATE signal and output the PPG signal. 
The PPG0 signal, PPG2 signal and PPG4 signal refer to the PPG signal that is output from ch.0, ch.2 and 
ch.4 of the PPG timer unit, respectively, and input to WFG. 
The CH10_PPG signal, CH32_PPG signal and CH54_PPG signal refer to the PPG signal that is used at 
WFG ch10, WFG ch32 and WFG ch54 respectively, whose input has been selected by WFSA.PSEL[1:0]. 
   Setting example 1) 
WFSA10.PSEL[1:0]=00, WFSA32.PSEL[1:0]=00, and WFSA54.PSEL[1:0]=00 selects the common use 
of ch.0 of the PPG timer unit at all the channels of WFG. 
GATE0 becomes the logic OR signal of CH10_GATE, CH32_GATE and CH54_GATE. Both GATE2 
and GATE4 are set to fixed Low output. Each channel of WFG instructs ch.0 of the PPG timer unit to 
start up. 
All of CH10_PPG, CH32_PPG and CH54_PPG become the PPG0 signal. Each channel of WFG uses the 
output signal of ch.0 of the PPG timer unit for waveform generation. 
   Setting example 2) 
WFSA10.PSEL[1:0]=00, WFSA32.PSEL[1:0]=01, and WFSA54.PSEL[1:0]=10 selects the individual 
use of ch.0, ch.2 and ch.4 of the PP G timer unit for each channel of WFG. 
GATE0=CH10_GATE, GATE2=CH32_GATE, and GATE4=CH54_GATE are output, separately. Each 
channel instructs ch.0, ch.2 or ch.4 of the PPG timer unit to start up, individually. 
CH10_PPG = PPG0, CH32_PPG=PPG2, and CH54_PPG=PPG4 are set. Each channel of WFG uses the 
output signal of the corresponding PPG timer unit for waveform generation. 
 
    WFSA.PSEL[1: 0

] is set d
 ifferently between MFTunit0 and MFTunit1 and the channel number of the 
PPG timer unit to be connected is also different. The descriptions above are intended for 
WFSA.PSEL[1:0] in MFTunit0. For information about MFTunit1, see  5.1 Connection of Model 
Co ntaini
n

g Multiple MFT’s . 
   To us e th

e GATE signal, the PPG timer unit must be set beforehand. For details, see the chapter PPG. 
   Even without the use of the GATE signal, the PPG timer unit can start outputting upon instruction by 
CPU. 
 
 
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4. Registers of Multifunction Timer 
 
[bit11:10] WFSA.PGEN[1:0] 
Process Value Function 
00 Does not reflect the CH_PPG signa l on WFG output (RTO output). 
Write 
Other 
than 
above  Specifies the condition to be used to reflect the CH_PPG signal on WFG 
output. 
For details of the reflection conditions, see 4.5
 Details of WFG Output 
Wa v e f o
r

m . 
Read  - Reads the register setting. 
 
WFSA.PGEN[1:0] is a register that  specifies how to reflect the CH_PPG signal that is input to each channel 
of WFG on WFG output, in combination with WFSA.TMD[2:0]. 
When WFG’s operation mode is set to Through mode, the CH_PPG signal can be output to the RTO pin 
without any change, according to the setting of WFSA.P GEN[1:0]. This register setting has no meaning, if 
WFSA.TMD[2:0] is set to 100, 111. Change the setting,  while OCU and PPG timer unit to be connected are 
stopping. 
[bit12] WFSA.DMOD 
Process Value  Function 
0 Sets the output polarity for the output of the non-overlap signal to normal 
polarity (Active High). 
Write 
1 Sets the output polarity of the non-overlap signal to reversed polarity 
(Active Low). 
Read 
- Reads the register setting. 
 
WFSA.DMOD is a register that specifi es which polarity will be used to output the non-overlap signal. 
In the case of WFSA.TMD[2:0]=100 or WFSA.TMD[2:0]= 111, the non-overlap signal is output for WFG’s 
RTO(0) and RTO(1) output. The output polarity can be se lected by this register setting. The register setting 
has no meaning, unless WFSA.TMD[2:0] is set to 100, 111. Change the setting, while OCU and PPG 
timer unit to be connected are stopping. 
[bit13] Reserved 
Process Function 
Write  0 must be written at write access. 
Read 0 is read. 
 
[bit15:14] Reserved 
Process Function 
Write  Writing is ignored. 
Read An undefined value is read. 
 
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4. Registers of Multifunction Timer 
 
4.3.11.  WFG Timer Value Register (WFTM) 
WFTM is a 16-bit register that sets the initial value of the WFG timer. 
Each mounted channel has three registers: WFTM10, WFTM32 and WFTM54. 
WFTM10 sets the initial value of the WFG timer for WFG ch10 (the output processing block of 
OCU ch1 and ch0). 
WFTM32 sets the initial value of the WFG timer for WFG ch32 (the output processing block of 
OCU ch3 and ch2). 
WFTM54 sets the initial value of the WFG timer for WFG ch54 (the output processing block of 
OCU ch5 and ch4). 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
 
Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field WFTM[15:0] 
Attribute R/W 
Initial  Va l u e   0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
  Functions of Register 
[bit15:0] WFTM.WFTM[15:0] 
Process Function 
Write  Sets the initial value of the WFG timer. Setting 0x0000 means 65536. 
Read Reads the register setting. 
 
WFTM[15:0] is a 16-bit register that sets the initial value of the WFG timer. 
The operating time of the WFG timer can be set  as shown below, according to the setting of WFTM. 
Operating time of WFG timer = WFTM value x Operation clock cycle of WFG timer 
When WFG’s operation mode is Timer PPG mode, RT dead timer mode or PPG dead timer mode 
(WFSA.TMD[2:0]=010, 100, 111), the WFG timer loads the initial value from the WFTM register, starts 
Down-count operation, when instru cted to start up, and then stops once the counting is completed. 
   In Timer PPG mode:   
WFG timer counts the time set in the WFG timer operation flag. 
   In RT dead timer mode and PPG dead timer mode: 
WFG timer counts the dead time of the non-overlap signal. 
When WFG’s operation mode is Through mode or RT-PPG mode (WFSA.TMD[2:0]=000, 001), the WFG 
timer is not used for generation of output waveforms. In these modes, therefore, it can be used as a reload 
timer that generates interrupts to CPU in the intervals set by WFTM. For information about how to use it as 
a reload timer, see  4.3.13 WFG Interrupt Control Register (WFIR). 
Th is register can
 b

e rewritten, regardless of whether the WFG timer is currently operating or stopping. 
A new value rewritten to this register becomes valid from the next startup of the timer. 
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4. Registers of Multifunction Timer 
 
4.3.12.  NZCL Control Register (NZCL) 
NZCL is a 16-bit register that controls DTIF interrupt (interrupt for emergency motor shutdown 
by signal input from the DTTIX pin). 
  It should be noted that this register does not allow for byte access. 
 Configuration of Register 
 
Bit 15 14 13 12 11 10 9 8 
Field Reserved 
Attribute - 
Initial Value  0 0 0  0 0 0 0 0 
           
Bit  7 6 5  4 3 2 1 0 
Field Reserved  SDTI NWS[2:0]  DTIE 
Attribute -  W R/W  R/W 
Initial Value 0 0 0  0 0 0 0 0 
 
  Functions of Register 
[bit0] NZCL.DTIE 
Process Value  Function 
0 Ignores the signal input from the DTTIX pin. Write 
1 Generates DTIF interrupt by signal input from the DTTIX pin. 
Read - Reads the register setting. 
 
NZCL.DTIE is a register that specifies whether or not to generate DTIF interrupt by signal input from the 
DTTIX pin. 
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4. Registers of Multifunction Timer 
 
Figure 4-7 shows a block diagram and time chart of the DTIX pin and DTIF interrupt. 
Figure 4-7 Block Diagram and Time Chart of DTIX Pin and DTIF Interrupt 
 
NZCL
Noise cancellerDTTIX
input portDTIF interrupt
RTO0 ～RTO5
GPIO
RTO0～RTO5
output portWFG
Interrupt controller
DTTIX input signal
DTIF interrupt
Noize cancel operation
RTO0~RTO5 port
MFT-RTO outputGPIO-Motor Stop level Output(Hiz)
▲DTIF Interrupt assert ▲DTIF interrupt clear
OCU
MFTMotor Stop level
MFT-RTO output
  
 The DTTIX pin is a special pin dedicated to inputting  an external interrupt signal for emergency motor 
shutdown. When the Low level is input, it recognizes  the signal as a request for emergency motor shutdown. 
The input signal of this pin is input to the noise canceler. If a Low-level pulse no less than the value set by 
the noise canceler is input, the WFIR.DTIF register is  set, the DTIF interrupt signal is asserted, and an 
interrupt is generated to CPU. 
The DTIF interrupt signal is connected to the interrupt controller and the I/O port selector. 
The I/O port selector can switch the state of the RTO0 to  RTO5 output pins to the setting state of the sharing 
GPIO port, while DTIF interrupt is being generated. 
The signal required for emergency motor shutdown can be  output to the RTO0 to RTO5 pins by setting the 
GPIO pin shared with the RTO0 to RTO5 pins to the motor non-operating level beforehand. 
The generated interrupt signal is deasserted by cl earing the WFIR.DTIF register (writing 1 to the 
WFIR.DTIC). 
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4. Registers of Multifunction Timer 
 
Ta b l e  4 - 5 shows a list of function se ttings of the GPIO p in. 
PFR, DDR and PDOR in the table refer to the corresponding  registers of the GPIO port that are shared with 
the RTO0 to RTO5 pins.   
Table 4-5 Setting List of Motor Non-operating Level by DTTIX Pin Interrupt 
Setting of GPIO Register 
 
PFR EPFR1 
[11:0]  EPFR1
[12]  DDRPDOR DTIF 
Signal  Level  State of RTO Pin 
0 
Output RTO0 to RTO5 1 1 
1 Output High level 
0 Output RTO0 to RTO5 1 0 
1 Output Low level 
0 Output RTO0 to RTO5 
When switching the 
output state of the 
pin by DTIF 
interrupt 
1 
0 don’t
care  1 Hi-Z state 
0 When not switching 
the output state of 
the pin by DTIF 
interrupt 
1 101010101010
Or 
010101010101
0 don’t
care  don’t
care  1 Output RTO0 to RTO5 
 
  PFR, EPFR1[11:0] is the basic setting for using the LSI pin as RTO output of MFT. 
   EPFR1[12] is a bit that specifies whether or not to switch the pin function by interrupt. 
   The EPFR1 register controls the pin used in MFTunit0. In the case of MFTunit1, the EPFR2 is used. 
   Setting the DDR, PDOR register specifies the motor non-operating level when the pin function is 
switched. 
 
If the output state is not to be switched by DTIF interrupt (EPFR1[12]=0), the state of the output pin is not 
switched, but DTIF interrupt is generated; therefore, CPU can receive interrupt notification. 
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4. Registers of Multifunction Timer 
 
[bit3:1] NZCL.NWS[2:0] 
Process Value Function 
000 DTIF interrupt is generated immediately after Low-leve input from the 
DTTIX pin. 
(No noise-canceling) 
001 
Sets the noise-canceling width to 4 PCLK cycles. 
010 Sets the noise-canceling width to 8 PCLK cycles. 
011 Sets the noise-canceling width to 16 PCLK cycles. 
100 Sets the noise-canceling  width to 32 PCLK cycles. 
Write 
Other than 
above  Setting prohibited 
Read 
- Reads the register setting. 
 
NZCL.NWS[2:0] is a register that sets the noise-ca nceling width of the noise-canceler for the DTTIX pin 
input signal. 
[bit4] NZCL.SDTI 
Process Value  Function 
0 Does nothing. Write 
1 Forcibly generates DTIF interrupt, rather than by NZCL.DTIE setting. 
Read - 0 is always read. 
 
NZCL.SDTI is a register that generates DTIF in terrupt by writing to the register via software. 
Writing 1 to this register sets the WFIR.DTIF and  generates interrupt, irrespective of NZCL.DTIE setting 
and the state of the DTTIX pin. Writing to this register  allows for the use of the output switch function for 
the RTO pin in the I/O port controller. The generate d interrupt signal is deasserted by clearing the 
WFIR.DTIF register (i.e. writing  1 to the WFIR.DTIC register). 
[bit15:5] Reserved 
Process Function 
Write  0 must be written at write access. 
Read 0 is read. 
 
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4. Registers of Multifunction Timer 
 
4.3.13.  WFG Interrupt Control Register (WFIR) 
WFIR is a register that controls DTIF interrupt and the interrupt from the WFG timer. 
This register is a special register dedicated to interrupt control, and each register bit is 
configured so that its state is not affected by writing 0. 
For this reason, reading before writing to the register is not required. Also, each register bit is 
configured so that its state is not affected by writing the read value back. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
 
Bit 15 14 13 12 11 10 9 8 
Field TMIS54TMIE54 TMIC54TMIF 54TMIS32TMIE32 TMIC32 TMIF32
Attribute W R/W W  R W R/W  W R 
Initial Value  0 0 0  0 0 0 0 0 
           
Bit  7 6 5  4 3 2 1 0 
Field TMIS10 TMIE10 TMIC10 TMIF10 Reserved  DTIC DTIF 
Attribute  W R/W W  R - W R 
Initial Value  0 0 0  0 0 0 0 0 
 
  Functions of Register 
[bit0] WFIR.DTIF 
Process Value  Function 
Write - Writing is ignored. 
0  Indicates that DTIF interrupt has not been generated. Read 
1 Indicates that DTIF interrupt has been generated. 
 
[bit1] WFIR.DTIC 
Process Value  Function 
0 Does nothing. Write 
1 Clears WFIR.DTIF and deassert s the DTIF interrupt signal. 
Read - 0 is always read. 
 
WFIR.DTIF is a register that ch ecks the state of DTIF interrupt. 
WFIR.DTIC is a register that  clears WFIR.DTIF and deasserts the DTIF interrupt signal. 
The WFIR.DTIF register is set by inputting the emer gency motor shutdown signal from the DTTIX pin or 
writing 1 to the NZCL.SDTI register.  When WFIR.DTIF is set, the DTIF interrupt signal is asserted and 
an interrupt is generated to CPU. 
Writing 1 to WFIR.DTIC clears WFIR.DTIF an d deasserts the DTIF interrupt signal. 
If interrupt processing has been performed by DTIF interrupt, make sure to clear DTIF when returning from 
the interrupt. 
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