Fujitsu Series 3 Manual

							 
4. Examples of USB Function Setting Procedures 
 
 Example control for packet  transfer in OUT direction 
 
[Initial settings]
Initial settings
- EP Control Register (EPxC) setting
- DRQIE:bit 14 of the EP Status Register (EPxS) = 1
End initial settings
[USB interrupt] Start USB interrupt
- Check by the SIZE bit of the Epx Status Register (EPxS)
NODMA transfer end flag = 1
YES
- USB data request bit (DRQ: bit 10 of the Epx 
Status Register (EPxS)) = 0 
- Dummy read of the relevant USB interrupt control  register
End interrupt
Set USB Endpoints
Enable USB interrupts
Clear USB interrupt flag +
Dummy read
Start DMAC by software Check receive data size
Set DMAC
  
 
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4. Examples of USB Function Setting Procedures 
 
 Example control for automatic data  size transfer in IN direction 
 
[Initial settings]
Initial settings
- EP Control Register (EPxC) setting- DMAE:bit 11 of the EP Control Register (EPxC) = 1
Notes:
Set USB interrupt level to the lowest
- DRQIE:bit 14 of the EP Status  Register (EPxS) = 1
End initial settings
[DMAtransfer end interrupt] Start DMA transfer end interrupt
End interrupt
Set interrupt level
(Resume the correlation between the  USB interrupt level and the DMAC 
interrupt level used by packet transfer  to that before the interrupt.)
Clear DMA transfer end interrupt Set DMAC
Set USB Endpoints
Set interrupt level
(Set USB interrupt level to the lowest)
Enable USB interrupts
  
 
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4. Examples of USB Function Setting Procedures 
 
 Example control for automatic data  size transfer in OUT direction 
 
[Initial settings]
Initial settings
- EP Control Register (EPxC) setting- DMAE:bit 11 of the EP Control Register (EPxC) = 1
Notes:
Set USB interrupt level to the lowest
End initial settings
[DMAtransfer end interrupt] Set DMAC
Set USB Endpoints
Set interrupt level
(Set USB interrupt level to the lowest)
Enable USB interrupts- DRQIE:bit 14 of the EP Status  Register (EPxS) = 1
Start DMA transfer end  interrupt
Clear DMA transfer end interrupt
Set interrupt level
(Resume the correlation between the  USB interrupt level and the DMAC  interrupt level used by packet 
transfer to that before the interrupt.)
End interrupt
  
 
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CHAPTER  20-2: USB Function 
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5. USB Function Registers 
 
5.  USB Function Registers 
This section explains the configuration and functions of the registers used for the USB 
function. 
 USB function register list 
Abbreviation Register  name See 
UDCC UDC Control Register  5.1 
EP0C EP0 Control Register  5.2 
EP1C EP1 Control Register  5.3 
EP2C EP2 Control Register  5.3 
EP3C EP3 Control Register  5.3 
EP4C EP4 Control Register  5.3 
EP5C EP5 Control Register  5.3 
TMSP Time Stamp Register  5.4 
UDCS UDC Status Register  5.5 
UDCIE UDC Interrupt Enable Register  5.6 
EP0IS EP0I Status Register  5.7 
EP0OS EP0O Status Register  5.8 
EP1S EP1 Status Register  5.9 
EP2S EP2 Status Register  5.9 
EP3S EP3 Status Register  5.9 
EP4S EP4 Status Register  5.9 
EP5S EP5 Status Register  5.9 
EP0DTH EP0 Data Register high-order  5.10 
EP0DTL EP0 Data Register low-order  5.10 
EP1DTH EP0 Data Register high-order  5.10 
EP1DTL EP0 Data Register low-order  5.10 
EP2DTH EP0 Data Register high-order  5.10 
EP2DTL EP0 Data Register low-order  5.10 
EP3DTH EP0 Data Register high-order  5.10 
EP3DTL EP0 Data Register low-order  5.10 
EP4DTH EP0 Data Register high-order  5.10 
EP4DTL EP0 Data Register low-order  5.10 
EP5DTH EP0 Data Register high-order  5.10 
EP5DTL EP0 Data Register low-order  5.10 
 
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5. USB Function Registers 
 
 UDCC.RST dependent register  bit update timing list 
 Register Bit 
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UDCC HCONTX, PFBK, PWC 
EP0C PKS0 
Register bits to be updated when 
UDCC.RST=1 
EP1C EPEN, TYPE, DIR, PKS1 
EP2C EPEN, TYPE, DIR, PKS2 
EP3C EPEN, TYPE, DIR, PKS3 
EP4C EPEN, TYPE, DIR, PKS4 
EP5C EPEN, TYPE, DIR, 

PKS5 
EP0IS BFINI, DRQI Register bits initialized when 
UDCC.RST=1 EP0OS BFINI, DRQ, SPK 
EP1S BFINI, DRQ, SPK (Update when UDCC.RST=0) 
EP2S BFINI, DRQ, SPK 
EP3S BFINI, DRQ, SPK 
EP4S BFINI, DRQ, SPK 
EP5S BFINI, DRQ, SPK 
TMSP TMSP 
UDCS SUSP, SOF, BRST, WKUP, SETP, CONF 
SUSPIE,

 SOFIE, BRSTIE, WKUPIE, CONFN, 
CONFIE 
UDCIE 
UDCC RESUME, USTP Register bits unaf
fected by UDCC.RST 
EP0C STAL 
EP1C DMAE, NULE, STAL 
EP2C DMAE, NULE, STAL 
EP3C DMAE, NULE, STAL 
EP4C DMAE, NULE, STAL 
EP5C DMAE, NULE, STAL 
EP1DTH/LBFDT 
EP2DTH/LBFDT 
EP3DTH/LBFDT 
EP4DTH/LBFDT 
EP5DTH/L BFDT 
 
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5. USB Function Registers 
 
5.1.  UDC Control Register (UDCC) 
The UDC Control Register (UDCC) controls the UDC core circuit. 
The following figure shows the bit configuration of the UDC Control Register (UDCC). bit  15 14  13 12  11 10  9 8 
FUJITSU SEMICONDUCTOR LIMITED 
Field  Reserved Reserved ReservedReserv

edReserved Reserved Reserved Reserved
Attribute  - -  - - -  - - - 
Initial value 0 0  0 0 0  0 0 0 
  bit  7 6 5 4  3 2 1 0 
Field RST  RESUM HCONX USTP STALCLREN Reserved RFBK  PWC 
Attribute R/W R/W R/W R/W  R/W - R/W R/W 
Initial value  1 0 1 0  0 0 0 0 
 
 
The UDC  Con

trol Register (UDCC), ex cept bit 6 RESUM
  and bit 4 USTP, should be configured while bit 7 
RST = 1, and should not be rewritten while USB is r unning. Bit 6 RESUM must be set or reset in USB 
suspend mode and while the remote wake-up is enabled by the following command. 
Set bit 4 USTP to 1 before stop mode or timer mode is entered. 
When those modes have been released, set the SUSP of UDCS and USTP of UDCC to 0 in this order after 
confirmation of stabili zed USB supply clock. 
 
The following explains the function of each  bit in the UDC Cont
 rol Register (UDCC). 
[bit 15:7] Reserved bits  These bits are reserved. Always write 0 to  these bits. They are always read as 0. 
[bit 7] RST: Function Reset Bit (function ReSeT)  This bit is ORed with the chip system reset to individually resets the USB function. The USB function is 
reset by the RST bit when connected with the host via  cable. As the initial value is 1, reset enabled, write 
0 to release the state. 
Bit Description 
0  Releases USB Function reset 
1  Resets the USB function 
 
 
This  b

it initializes the relevant bit of the Time Stamp Register, UDC Status Register, Interrupt Enable 
Register at the same tim e. It also set

s the BFINI of the EP0I, EP0O, and EP1 to 5 Status Register 
concurrently. After the initial settings, therefore, clear th e RST bit (BFINI is not cleared) and clear BFINI of 
the Endpoints used in this order.   
 
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5. USB Function Registers 
 
[bit 6] RESUM:    Resume Setting Bit (RESUMe set) 
In suspend state while remote wake-up is enabled *,  the resume is started when writing 1 to the RESUM 
bit. To instruct to resume, set the RESUM bit to 1, and then write 0 to it to clear. 
* :  The DEVICE_REMOTE_WAKEUP bit is set by the SET_FEATURE command from the host. 
Bit Description 
0  Resets the USB resume start instruction bit 
1 Instructs to start the USB resume 
 
[bit 5] HCONX: Host Connection Bit (Host CONnection)  This bit controls the switch between an external pull-up resistor and the USB data line to make the 
connection with the host or hub recognized. 
Bit Description 
0  Connected to the host or hub 
1  Disconnected from the host or hub 
 
 
Even  i

f the connection is found by the host or hub wh ile the external p
 ull-up resistor is kept ON, the bus 
reset command on the USB bus is ignored while this bit is 1. 
 
[bit 4] USTP: USB Operating Clock Stop Bit (Udc SToP)  Setting this  b

it stops the clock for the USB operating unit. When USB is not operated, power consumption 
can be reduced by configuring this bit. 
Bit Description 
0 Normal mode 
1  Stops the clock for the USB operating unit 
 
 
If stop  m

ode and timer mode is not set, the USTP bit must be configured after setting RST to 1, and also 
after 3 cycles at f u

ll speed or 43 cycles at low speed (supported only in host mode) so that the reset can be 
ensured.This bit can be cleared at  the same time RST is cleared. 
 
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5. USB Function Registers 
 
[bit 3] STALCLREN: Endpoint 1 to 5 STAL Bit Clear Select Bit (STALl CLeaR Enable) 
This bit selects the method to clear the STAL bit of Endpoint 1 to Endpoint 5 using the Clear Feature 
command. The STALCLREN bit sets whether to automatically clear the STAL bit to 0 by hardware, a bit 
of EP1 to EP5 Control Registers (EP1C to EP5C) for Endpoints (1 to 5) specified by the Clear Feature 
command This bit selects the method to clear the STAL bit of the Endpoint Control Registers (EP1C to 
EP5C), either by software or hardware. 
Bit Description 
0  Clears the STAL bit of the EP1 to EP5 Control Registers (EP1C to EP5C) by software.
Automat ically clears the STAL bit of the EP1 to EP5 Control Registers (EP1C to 
EP5C) by hardware. 
1 
 
 
The ST ALCLREN b

it should be configured while the  RST of the UDC Contro
 l Register (UDCC) is 1, 
and should not be rewritten while USB is running. 
 
[bit 2] Reserved bit  This bit is reserved . 

Always write 0 to this bit. It is always read as 0. 
 
[bit 1] RFBK: Data Toggle Mode Select Bit (Rate Feed BacK mode)  This bit selects the data toggle mode for USB interrupt transfer. 
Bit Description 
Selects the alternating d ata tog gle mode. 
0  Toggles data PID when the transfer has finished successfully. 
Selects the data to gg le mode. 
1  Unconditionally toggles data PID. 
 
[bit 0] PWC: Power Control Bit (PoWer Control)  This bit specifies the operating power mode (self power or bus power) of the USB function. 
(Configuration of this bit applies to standard command GetStatus.) 
Bit Description 
0 Bus power 
1 Self power 
 
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5. USB Function Registers 
 
5.2.  EP0 Control Register (EP0C) 
The EP0 Control Register (EP0C) controls Endpoint 0. 
The following figure shows the bit configuration of the EP0 Control Register (EP0C). bit 15 14 13 12 11 10 9 8 
Field - - - - ReservedReserved STAL Reserved
Attribute  - - -  - - - R/W - 
Initial value  X X X  X 0 0  0 0 
  bit  7 6 5  4 3 2 1 0 
Field Reserved PKS0 
Attribute - R/W R/W  R/W R/W R/W  R/W R/W 
Initial value 0 1 0  0 0 0 0 0 
 
 
Except  bi

t 9 STAL, the EP0 Control Register (EP0C) must  be configured wh
 ile both of the bit 7 RST in the 
UDC Control Register (UDCC) and bit 7 BFINI in the EP0I/O Status Register (EP0I/OS) are 1. It must 
not be rewritten while USB is running. 
 
The following explains the function of each bit in the EP0 Control Register (EP0C). 
[bit 15:12] Undefined bits  The written v

alue has no effect. The read value is undefined. 
 
[bit 11:10] Reserved bits  These bits are reserved. Always write 0 to these bits. 
They are always read as 0. 
 
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5. USB Function Registers 
 
[bit 9] STAL: Endpoint 0 Stall Setting Bit (STALl ep0 set) This bit can set Endpoint 0 to the STALL state (STALL response). 
This bit is cleared by hardware. If  a SETUP packet is received by End point 0 after the STALL response to 
Endpoint 0 is performed, this bit is cleared to 0. For the timing to clear this bit, see    STAL bit clear 
ti ming
 of  3.8 STALL  res

ponse/release of endpoint 0. 
Bit Description 
0 Ignored 
1  Sets the STALL state (STALL response) 
 
 
  If th e ST

ALCLREN bit of the USB Enable Register  (USBEN) is
  0, the STALL response remains 
operating to the host while the STAL bit is set to 1 .Upon the receipt of a normal SETUP packet after 
STAL bit reset, Endpoint 0 resumed from the STALL state. 
   A read-modify-write instruction read this bit as 0. 
 
[bit 8:7] Reserved bits  These bits are reserved . 

Write value should always be 0. 
They are always read as 0. 
 
[bit 6:0] PKS0: Packet Size Endpoint 0 Setting Bits (PacKet Size ep0 set)  These bits specify the maximum number of bytes transferred by one packet. For Endpoint 0, the maximum 
number of bytes is 64, and the set value is valid both for IN and OUT directions. 
Example: 0x08 => 8 bytes, 0x40 => 64 bytes (maximum value) 
 
  These bits m u

st be configured when both of the  RST bit in the 
 UDC Control Register (UDCC) and the 
BFINI bit in the EP0I/O Status Register (EP0I/OS ) are 1. Do not rewrite while USB is running. 
   A value exceeding the maximum number of transferable  bytes (0x40), and 0x00 must not be written. 
 
 
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