Fujitsu Series 3 Manual

							 
5. Registers 
 
[bit 11] ESCE: External trigger analog input selection bit This bit selects whether the external trigger analog input is selected with the P1A [2:0] bits in the Priority 
Conversion Input Selection Register (PCIS)  or the external input pin ECS [2:0] bits. 
Bit Description 
0 The external trigger analog input s are selected with P1A [2:0]. 
1 The external trigger analog inputs are selected with an external input. 
 
 
It is not  p

ossible to change the setting of the ESCE bit during A/D conversion. To change the setting, make 
sure th e 

A/D conversion is stopped. 
If channel selection with external pins ECS [2:0] cannot be used due to the product specifications, be sure to 
set the ESCE bit to 0. 
  [bit 10] PEEN: Priority conversion external start enable bit  Set this bit to 1 to start pri o

rity conversion using a falling edge of an external trigger pin input. 
Conversion started with an external trigge r has priority level 1 (highest priority). 
Bit Description 
0 External trigger start disable 
1 External trigger start enable 
 
[bit 9] PHEN: Priority conversion timer start enable bit  Set this bit to 1 to start priority conversion using a rising edge from a timer. Software startup (PSTR = 1) 
is valid even when this bit is set to 1. Conversion  started with an external trigger has priority level 2 
(lower than level 1). 
Bit Description 
0  Timer start disable 
1 Timer start enable 
 
[bit 8] PSTR: Priority conversion start bit  Setting this bit to 1 starts A/D conversion. Conversion  started with this bit has priority level 2 (lower than 
level 1). It is not possible to restart the conversion started with this bit. 
Description Bit  Read Write 
0 No  effect. 
1 The value is always 0. 
Starts priority conversion. 
 
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5. Registers 
 
5.8.  Priority Conversion FIFO Stage Count Setup Register (PFNS) 
The Priority Conversion FIFO Stage Count Setup Register (PFNS) sets up the generation of 
interrupt requests in priority conversion. When the specified count of FIFO stages store A/D 
conversion data, the interrupt request bit (PCIF) is set. 
 
bit 7 6 5 4 3 2 1 0 
Field Reserved TEST [1:0] Reserved PFS [1:0] 
Attribute  - -  R R  - -  R/W R/W 
Initial value  X X X  X X X  0 0 
 
[bit 7:6] Reserved: Reserved bits 
Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 5:4] TEST [1:0]: Test bits  Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 3:2] Reserved: Reserved bits  Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 1:0] PFS [1:0]: Priority conversion FIFO stage count setting bits  When A/D conversion data for the FIFO stage count (N  + 1) set in PFS [1:0] is written, the interrupt request 
flag (PCIF) is set to 1. 
Bit [1:0]  Description 
0b00 Generates an interrupt request when convers
ion result is stored in the first FIFO 
stage. 
0b01  Generates an interrupt request when conve
rsion result is stored in the second 
FIFO stage. 
0b10  Generates an interrupt request when convers
ion result is stored in the third FIFO 
stage. 
0b11  Generates an interrupt request when convers
ion result is stored in the fourth FIFO 
stage. 
 
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5. Registers 
 
5.9.  Priority Conversion FIFO Data Register (PCFD) 
The Priority Conversion FIFO Data Register (PCFD) consists of four FIFO stages and stores 
analog conversion results. Data can be retrieved sequentially by reading the register. 
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field PD11 PD10 PD9  PD8 PD7 PD6PD5PD4PD3PD2PD1PD0Reserved 
Attribute R R R  R R R R R R R R R R R R R 
Initial 
value  X X X X X X X X X X X X X X X X 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved  INVL Reser
ved  RS2
RS1RS0 Reserved  PC4PC3 PC2 PC1 PC0
Attribute R R R  R R R R R R R R R R R R R 
Initial 
value  X X X X X X X X X X X X X X X X 
  [bit 31:20] PD11:PD0: Priority conversion result  The result of 12-bit priority A/D conversion is written. 
 
[bit 19:13] Reserved: Reserved bits  The read value is undefined. 
 
[bit 12] INVL : A/D conversion result disable bit  This bit is set when this register value is invalid. 
Bit Description 
0  This register value is valid 
1 This register value is invalid 
 
[bit 11] Reserved: Reserved bit  The read value is undefined. 
 
[bit 10:8] RS2:RS0 : Scan  conversion start factor 
The start factor of the priority  conversion corresponding to this register value is shown. 
Bit [10:8]  Description 
0b001 Software start (priority level 2) 
0b010 timer start (priority level 2) 
0b100 External trigger (priority level 1) 
 
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5. Registers 
 
[bit 7:5] Reserved: Reserved bits The read value is undefined. 
 
[bit 4:0] PC4:PC0: Conversion input channel bits  The analog input channels corresponding to the conversion result written in PD11 to PD0 are written. 
Settings for channels not defined in the product speci fications are not written. See the specified number of 
the analog input channels in th e Data Sheet of each product. 
Bit [4:0]  Description 
0b00000 ch.0 
0b00001 ch.1 
0b00010 ch.2 
... ... 
0b11101 ch.29 
0b11110 ch.30 
0b11111 ch.31 
 
 
This  reg

ister has different bit configurations depending on the FDAS bit setting in the A/D Status Register 
(ADSR). When the FDAS b it is 1

, see 3.3.6 Bit placement selection for FIFO data registers . 
To perform a byte access to t h

is register, read the mo st significant byte (bit 31:24) to shift the FIFO data. 
Reading the other bytes (bit 23:16, b it 15:8, bit 7:0) does not shift FIFO. To perform  a half word access to 
this register, read the most significant half word (bit 31:16) to shift FIFO. Reading the other byte (bit 15:0) 
does not shift FIFO. Performing a word access to this register shifts FIFO. 
If software and a timer are started simultaneously, 0b011 may be read from the RS2:RS0 bit. 
Conversion started with an external trigger can be performed only when the analog input channel is 
between ch.0 to 7. 
 
 
 
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5. Registers 
 
5.10.  Priority Conversion Input Selection Register (PCIS) 
The Priority Conversion Input Selection Register (PCIS) is used to select the analog input 
channels for which priority conversion is performed. For software or timer start at priority level 
2, only one channel can be selected from multiple analog input channels. For external trigger 
start at priority level 1, one channel can be selected from eight channels (ch.0 to ch.7). 
 bit 7 6 5 4 3 2 1 0 
Field P2A [4:0] P1A [2:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7:3] P2A [4:0]: Priority level 2 analog input selection  This bit specifies the analog input channel for a start at  priority level 2 (software/timer). It can be selected 
from all channels. It is not possible to set the channel that is not defined in the product specifications. See 
the specified number of the an alog input channels in the Data Sheet of each product. 
Bit [7:3]  Description 
0b00000 ch.0 
0b00001 ch.1 
0b00010 ch.2 
... ... 
0b11101 ch.29 
0b11110 ch.30 
0b11111 ch.31 
 
[bit 2:0] P1A [2:0]: Priority level 1 analog input selection  This bit specifies the analog  input channel for a start at priority level  1 (external trigger). It can be selected 
from eight channels (ch.0 to ch.7). 
Bit [2:0]  Description 
0b000 ch.0 
0b001 ch.1 
0b010 ch.2 
... ... 
0b101 ch.5 
0b110 ch.6 
0b111 ch.7 
 
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5. Registers 
 
5.11.  A/D Comparison Value Setup Register (CMPD) 
The A/D Comparison Value Setup Register (CMPD) sets the value to be compared with the 
A/D conversion result. When the conditions set in both this register and the A/D Comparison 
Control Register (CMPCR) are satisfied, the conversion result comparison interrupt request 
bit (CMPIF) in the A/D Control Register (ADCR) is set. 
 bit 31 30 29 28 27 26 25 24 
Field CMAD11CMAD10 CMAD9CMA D8CMAD7CMAD6 CMAD5 CMAD4
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
  bit  23 22 21  20 19 18 17 16 
Field CMAD3 CMAD2  Reserved 
Attribute R/W R/W  - - - -  - - 
Initial value 0 0 X  X X X  X X 
 
[bit 31:22] CMAD11:CMAD2: A/D conversion result value setting bits  These bits set the value to be compar ed with the A/D conversion result. 
The most significant 10 bits (bit 11:2) of the A/D co nversion result are compared with the value in this 
register (CMAD11 to CMAD2). The l east significant two bits (bit 1 and 0) of the A/D conversion result are 
not compared. 
 
[bit 21:16] Reserved: Reserved bits  The read value is undefined. 
 
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5. Registers 
 
5.12.  A/D Comparison Control Register (CMPCR) 
The A/D Comparison Control Register (CMPCR) controls the A/D comparison function. When 
the converted value is compared with the value in the A/D Comparison Value Setup Register 
(CMPD) and the comparison condition in this register is satisfied, the conversion result 
comparison interrupt request bit (CMPIF) in the A/D Control Register (ADCR) is set. 
 bit 7 6 5 4 3 2 1 0 
Field CMPENCMD1 CMD0 CCH [4:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] CMPEN: Conversion result comparison function operation enable bit  This bit enables the operation of the A/D comparison function. 
Bit Description 
0  Stops the comparison function operation. 
1 Enables the comparison function operation. 
 
[bit 6] CMD1: Comparison mode 1  This bit sets the condition for gene rating a conversion interrupt request. 
Bit Description 
0 Generates an interrupt request when the most significant 10 bits (bit 11:2) of the 
A/D conversion result is smaller than the CMPD set value. 
1 Generates an interrupt request when the most significant 10 bits (bit 11:2) of the 
A/D conversion result is equal to or greater than the CMPD set value. 
 
[bit 5] CMD0: Comparison mode 0  This bit selects the comparison target. When this bit is 1, the setting of CCH [4:0] is invalid. 
Bit Description 
0  Compares the conversion result of  the channel set in CCH [4:0]. 
1 Compares the conversion  results of all channels. 
 
[bit 4:0] CCH [4:0]: Comparison target analog input channel  This bit sets the analog channel to be compared. When the CMD0 bit is 1, setting of this bit is invalid. It 
is not possible to set the channel that is not defined in the product specifications. See the specified number 
of the analog input channels in  the Data Sheet of each product. 
Bit [4:0]  Description 
0b00000 ch.0 
0b00001 ch.1 
0b00010 ch.2 
... ... 
0b11101 ch.29 
0b11110 ch.30 
0b11111 ch.31  
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5. Registers 
 
5.13.  Sampling Time Selection Register (ADSS) 
The Sampling Time Selection Register (ADSS3 to 0) allows you to set the sampling time for 
each bit. Which of the sampling times set in Sampling Time Setup Registers 0 and 1 (ADST0 
and 1) is used is specified in this register.   
 ADSS3 (most significant byte: TS31 to  TS24) and ADSS2 (least significant 
byte: TS23 to TS16) 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field TS31 TS30 TS29 TS28  TS27 TS26TS25TS24TS23TS22TS 21TS20 TS19 TS18 TS17TS16
Attribute R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
  [bit 15:0] TS31:TS16: Sampling time selection bits  Set the sampling time specified in the Sampling Time Se tup Register (ADST) for the corresponding channel. 
Setting 0 specifies the time set in ADST0 and setting 1  specifies the time set in ADST1. TS31 to TS16 
correspond respectively  to ch.31 to ch.16. 
 ADSS1 (most significant byte: TS15 to  TS8) and ADSS0 (least significant 
byte: TS7 to TS0) 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field TS15 TS14 TS13 TS12 TS11 TS10TS9TS8TS7TS6TS5TS4TS3 TS2 TS1TS0
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
  [bit 15:0] TS15:TS0: Sampling time selection bits  Set the sampling time specified in the Sampling Time Se tup Register (ADST) for the corresponding channel. 
Setting 0 specifies the time set in ADST0 and setting  1 specifies the time set in ADST1. TS15 to TS0 
correspond respectivel y to ch.15 to ch.0. 
 
It is not  p

ossible to write to the ADSS register during A/D conversion. 
It is not possib l

e to set 1 in the bit corresponding to a channel that is not defined in the product 
specifications. See the specified numbe r of the analog input channels in the Data Sheet of each product. 
 
 
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5. Registers 
 
5.14.  Sampling Time Setup Register (ADST) 
Sampling Time Setup Registers 0 and 1 (ADST0 and 1) set the sampling times for A/D 
conversion. ADST0 and 1 are provided for setting two sampling times, and which one is used 
is selected in the Sampling Time Selection Register (ADSS3 to 0). 
 ADST0 (most significant byte) 
 
bit 15 14 13 12 11 10 9 8 
Field STX02 STX01 STX00 ST04 ST03 ST02  ST01 ST00 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  1 0 0 0 0 
 
[bit 15:13] STX02:STX00: Sampling time N times setting bits  These bits multiply the sampling time set values in the ST04 to ST00 bits by N. 
Bit 15  Bit 14 Bit 13  Description 
0 0 0 Set value x 1 
0  0 1 Set value x 4 
0  1 0 Set value x 8 
0  1 1 Set value x 16 
1  0 0 Set value x 32 
1  0 1 Set value x 64 
1  1 0 Set value x 128 
1  1 1 Set value x 256 
 
[bit 12:8] ST04:ST00: Sampling time setting bits  These bit set the sampling time for A/D conversion. 
Sampling time = HCLK cycle × {(ST set value + 1) × STX setting multiplier + 1} 
Example:  When ST04 to ST00 = 9, STX02, STX01, and STX00 = 001 (multiplied by 4), and    HCLK = 80 MHz (12.5 ns),   
Sampling time = 12.5 ns × {(9 + 1) × 4 + 1} = 512.5 ns 
 
It is not  p

ossible to write to the ADST0 register  d
 uring A/D conversion. 
When STX02, STX01, and STX00 = 000 (ST04 to ST00  set values multiplied by 1) are set, set ST04 to 
ST00 to 3 or more (2 or less must not be set). 
For setting the sampling time, refer to the Electrical Characteristics in the data sheet to make sure that an 
appropriate time should be selected in accordance with an external im pedance of an input channel, an 
analog power supply voltage (AVCC),  and a base clock (HCLK) cycle.   
 
 
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5. Registers 
 
 ADST1 (least significant byte) 
 
bit 7 6 5 4 3 2 1 0 
Field STX12 STX11 STX10 ST14 ST13 ST12 ST11 ST10 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  1 0 0 0 0 
 
[bit 7:5] STX12:STX10: Sampling time N times setting bits  These bits multiply the sampling time set values in the ST14 to ST10 bits by N. 
Bit 7  Bit 6 Bit 5  Description 
0 0 0 Set value x 1 
0  0 1 Set value x 4 
0  1 0 Set value x 8 
0  1 1 Set value x 16 
1  0 0 Set value x 32 
1  0 1 Set value x 64 
1  1 0 Set value x 128 
1  1 1 Set value x 256 
 
[bit 4:0] ST14:ST10: Sampling time setting bits  These bit set the sampling time for A/D conversion. 
Sampling time = HCLK cycle × {(ST set value + 1) × STX setting multiplier + 1} 
Example:  When ST14 to ST10 = 9, STX12, STX11, and STX10 = 001 (multiplied by 4), and    HCLK = 80 MHz (12.5 ns),   
Sampling time = 12.5 ns × {(9 + 1) × 4 + 1} = 512.5 ns 
 
It is not  p

ossible to write to the ADST1 register  d
 uring A/D conversion. 
When STX12, STX11, and STX10 = 000 (ST14 to ST10  set values multiplied by 1) are set, set ST14 to 
ST10 to 3 or more (2 or less must not be set). 
For setting the sampling time, refer to the Electrical Characteristics in the data sheet to make sure that an 
appropriate time should be selected in accordance with an external im pedance of an input channel, an 
analog power supply voltage (AVCC),  and a base clock (HCLK) cycle.   
 
 
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CHAPTER  18-3: 12-bit  A/D Converter 
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