Fujitsu Series 3 Manual

							 
4. Registers of Multifunction Timer 
 
 Up/Down-count Mode (Active-High) 
When Up/Down-count mode (Active-High) is selected, the following operation applies. 
If FRT is up-counting, the output level of RT(0) signa l is changed to Active level (High), when FRT’s count 
value matches OCCP(0). If FRT is  down-counting, the output level is changed to Inactive level (Low), 
when FRT’s count value matches OCCP(0). When 0x0000 is set to OCCP(0), all-active (High) is output, 
and then, it returns to Inactive level (Low), when a value other than 0x0000 is set. As long as 0xFFFF is 
set to OCCP(0), the Inactive level (Low) is output. 
The operation of the RT(1) signal output is the same  as for RT(0) according to the value in OCCP(1). 
In this mode, OCU-ch.(0) and ch.(1) can operate inde pendently from each other. 
Figure 4-17  shows an example of the operation waveform when OCU-ch.1 is in Up/Down-count mode 
(Activ e-High). 
Th

is figure is based on the conditions that the buffer function of the OCCP register is 
enabled and the Zero valu e transfer is selected. 
Figure 4-17 Example of Operation Waveform  in OCU Up/Down-count Mode (Active-High) 
 
OCU wave form : Example of up-down-count mode  （ ch.1, Active-High, OCSA.BDIS1=0, OCSB.BTS1=0)
OCCP1 Buf. reg. FRT count
0x0000
Peak(=TCCP)
Value1
Value2
RT1 output
Value1Value2≧Peak0xffff0x00000xFFFF
OCCP1 reg.
Value1Value2≧ Peak0x00000xFFFF
 
 
 
Notes on  

Up/Down-count mode (Active-High) are as follows: 
   In this  m

ode, enable the buffer function of OCCP and select Zero value transfer for use. 
   If 0x0000 is set to OCCP register when OCU’s oper ation is enabled, the output level is changed to 
Active level immediately, regardless of FRT’s count value. 
   If a value no less than the Peak value of FRT’s counter is set to OCCP, the output level does not change, 
even when FRT’s counter value reaches its peak valu e. Also, the IOP0 and IOP1 registers are not set. 
 
 
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4. Registers of Multifunction Timer 
 
 Up/Down-count Mode (Active-Low) 
When Up/Down-count mode (Active- Low) is selected, the following operation applies. 
If FRT is up-counting, the output level of RT(0) signa l is changed to Active level (Low), when FRT’s count 
value matches OCCP(0). If FRT is  down-counting, the output level is changed to Inactive level (High), 
when FRT’s count value matches OCCP(0). When 0x000 0 is set to OCCP(0), all-active (Low) is output, 
and then, it returns to Inactive level (High), when a value other than 0x0000 is set. As long as 0xFFFF 
is set to OCCP(0), the Inactive level (High) is output. 
The operation of the RT(1) signal output is the same  as for RT(0) according to the value in OCCP(1). 
In this mode, OCU-ch.(0) and ch.(1) can operate inde pendently from each other. 
Figure 4-18  shows an example of the operation waveform when OCU-ch.0 is in Up/Down-count mode 
(Activ e-Low). This 
figu

re is based on the conditions  that the buffer function of the OCCP register is 
enabled and the Zero value  transfer is selected.   
Figure 4-18 Example of Operation Waveform  in OCU Up/Down-count Mode (Active-Low) 
 
OCU wave form : Example of up-down-count mode  （ ch.0, Active-Low, OCSA.BDIS0=0, OCSB.BTS0=0)
OCCP0 Buf. reg. FRT count
0x0000
Peak(=TCCP)
Value1
Value2
RT0 output
Value1Value2≧Peak0xffff0x00000xFFFF
OCCP0 reg.
Value1Value2≧ Peak0x00000xFFFF
 
 
 
Notes

 on Up/Down-count mode  (Active-Low) are as follows: 
   In t h

is mode, enable the buffer function of OCCP and select Zero value transfer for use. 
   If 0x0000 is set to OCCP register when OCU’s oper ation is enabled, the output level is changed to 
Active level immediately, regardless of FRT’s count value. 
   If a value no less than the Peak value of FRT’s counter is set to OCCP, the output level does not change, 
even when FRT’s counter value reaches its peak valu e. Also, the IOP0 and IOP1 registers are not set. 
 
 
 
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CHAPTER  15: Multifunction  Timer 
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4. Registers of Multifunction Timer 
 
4.5.  Details of WFG Output Waveform 
This section provides details of the output waveform in each mode of WFG. 
 List of WFG Operation Modes 
Ta b l e  4 - 9  shows a list of WFG operation modes, register settings and CH_GATE signal outputs. 
Table 4-10  shows a list of WFG operation modes, register settings, RTO(1) and RTO(0) signal outputs. 
Table 4-9 List of Details of CH_GATE Signal Outputs 
Operation Mode  WFSA.
TMD[2:0] WFSA. 
GTEN[1:0]  CH_GATE Signal Output 
Through mode 
000 don’t care  Always outputs Low-level signals 
00  Always outputs Low-level signals 
01  Outputs RT(0) without change 
10 Outputs RT(1) without change RT-PPG mode  001 
11 Outputs High-level signals when either RT(1) or RT(0) signal is High-level
Outputs Low-level signals when both RT(1) and RT(0) signals are 
Low-level 
00 
Always outputs Low-level signals 
01  Outputs WFG timer active flag0 
10 Outputs WFG timer active flag1 Timer-PPG mode  010 
11 Outputs High-level signals when eith
er of WFG timer active flags is 1 
Outputs Low-level signals when both of WFG timer active flags are 0 
RT dead timer  mode  100 don’t care Always outputs Low-level signals 
00 
Always outputs Low-level signals 
01  Outputs RT(0) without change 
10 Outputs RT(1) without change PPG dead timer 
mode  111 
11 Outputs High-level signals when either RT(1) or RT(0) signal is High-level
Outputs Low-level signals when both RT(1) and RT(0) signals are 
Low-level 
* The CH_GATE signals in the table refer to CH10_GATE, CH32_GATE and CH54_GATE before being 
selected by WFSA.PSEL[1:0] , as shown in the diagram of WFG-PPG connection. 
 
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4. Registers of Multifunction Timer 
 
Table 4-10 List of Output Details of RTO Pin 
Operation Mode  WFSA. 
TMD [2:0]  WFSA.
PGEN [1:0]  WFSA. 
DMOD  Output of RTO(1) Signal 
Output of RTO(0) Signal 
00 Outputs RT(1) signal through  Outputs RT(0) signal through 
01 Outputs RT(1) signal through  Outputs CH_PPG signal through 
10 Outputs CH_PPG signal through  Outputs RT(0) signal through 
Through 
mode  000 
11 don’t 
care 
Outputs CH_PPG signal through  Outputs CH_PPG signal through 
00 Outputs RT(1) signal through  Outputs RT(0) signal through 
01 Outputs RT(1) signal through  (*A) 
Outputs Low-level signals when RT(0) 
is Low-level   
Outputs CH_PPG signal when RT(0) 
signal is High-level 
10 (*B) 
Outputs Low-level signals when 
RT(1) signal is Low-level 
Outputs CH_PPG signal when RT(1) 
signal is High-level  Outputs RT(0) signal through 
RT-PPG 
mode  001 
11 don’t 
care 
Same as *B Same as *A 
00  (*D) 
Outputs Low-level signals when 
WFG timer active flag1 is 0 
Outputs High-level signals when 
WFG timer active flag1 is 1  (*C) 
Outputs Low-level signals when WFG 
timer active flag0 is 0 
Outputs High-level signals when WFG 
timer active flag0 is 1 
01 
Same as *D  (*E) 
Outputs Low-level signals when WFG 
timer active flag0 is 0   
Outputs CH_PPG signal when WFG 
timer active flag0 is 1 
10 (*F) 
Outputs Low-level signals when 
WFG timer active flag1 is 0 
Outputs CH_PPG signal when WFG 
timer active flag1 is 1  Same as *C 
Timer-PPG 
mode  010 
11 don’t 
care 
Same as *F Same as *E 
0 Starts WFG timer at the rising and 
falling edges of the RT(1) signal and 
generates the non-overlap signal. 
Outputs the generated non-overlap signa l with normal polarity (Active High) RT  
RT dead 
timer mode  100 
don’t 
care 
1 Starts WFG timer at the rising and 
falling edges of the RT(1) signal and 
generates the non-overlap signal. 
Outputs the generated non-ove rlap signal with reversed polarity (Active Low) 
0 Starts WFG timer at the rising and fa
lling edges of the CH_PPG signal and 
generates the non-overlap signal. 
Outputs the generated non-overlap signa l with normal polarity (Active High) 
PPG dead 
timer mode  111 don’t 
care 
1 Starts WFG timer at the rising and fa
lling edges of the CH_PPG signal and 
generates the non-overlap signal. 
Outputs the generated non-ove rlap signal with reversed polarity (Active Low) 
* The CH_PPG signals in the table refer to CH10_PPG, CH32_PPG and CH54_PPG selected by 
WFSA.PSEL[1:0], as shown in the diagram of WFG-PPG connection. 
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4. Registers of Multifunction Timer 
 
 Through Mode 
The operation in Through mode is as follows (see the List of Output Details). 
The output of the CH_GATE signal is always fixed to the Low level. 
The RTO(1) and RTO(0) signals output the RT(1), RT(0), and CH_PPG signals through without change by 
PGEN[1:0] setting. 
Figure 4-19  shows an example of the operation waveform in Through mode of WFG-ch.10. In this example, 
th e RT0 signal an

d the CH10_PPG signal are output through to RTO0 and RTO1, respectively (PPG timer 
unit can start outputting without the use of the GATE signal). 
Figure 4-19 Example of Operation Waveform in WFG-Through Mode 
 
CH10_PPG
RTO0
CH10_GATE(Low
）
WFG wave form : Example of through mode ( ch.10,  WFSA10.PGEN=10 )
RT0
RTO1
  
 
  RT-PPG Mode 
The operation in RT-PPG mode is as follows (see the List of Output Details). 
The CH_GATE signal outputs the RT(1) signal, RT(0) si gnal or the logic OR signal of each signal by 
GTEN[1:0] setting. 
The RTO(1) and RTO(0) signals output the RT(1) signa l, RT(0) signal, CH_PPG signal, or the logic AND 
signal of each signal by PGEN[1:0] setting. 
Figure 4-20  shows an example of the operation waveform in  RT-PPG
 m
 ode of WFG-ch.10. In this example, 
the CH0_GATE signal is generated from both RT1 and RT0 to start PPG-ch.0. The CH0_PPG signal is 
superimposed on RTO0 and RTO1 to output. 
Figure 4-20 Example of Operation Waveform in WFG-RT-PPG Mode 
 
WFG wave form: Example of RT-PPG mode  ( ch.10, WFSA10.GTEN=11, WFSA10.PGEN=11)
RT0
CH10_PPG RTO0
CH10_GATE
RT1
RTO1  
 
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CHAPTER  15: Multifunction  Timer 
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4. Registers of Multifunction Timer 
 
 Timer PPG Mode 
The operation in Timer-PPG mode is as follows (see the List of Output Details). 
Each channel of WFG has two flags: WFG timer ac tive flag0 and WFG timer active flag1. This mode 
outputs a waveform using these flags. 
The CH_GATE signal outputs WFG timer active flag1,  WFG timer active flag0, or the logic OR signal of 
each signal by GTEN[1:0] setting. 
The RTO(1) and RTO(0) signals output these active fl ags, CH_PPG signal, or the logic AND signal of each 
signal by PGEN[1:0] setting. 
Figure 4-21  shows Example 1 of the operation waveform in Timer PPG mode of WFG-ch.10. 
Figure 4-21 Example 1 of Operation Waveform in WFG-Timer PPG Mode 
 
WFG wave form : Example1 of Timer-PPG mode ( ch.10, WFSA.GTEN=11, WFSA10.PGEN=11
RT0
CH10_PPG RTO0
CH10_GATE
RT1
RTO1
WFG10 timer count
WFG timer active flag 0
WFG timer active flag 1
  
 
The WFG timer active flags operate as follows: 
WFG timer active flag0 is set to 1, when the rising edge of the RT(0) signal is detected. 
WFG timer active flag1 is set to 1, when the rising edge of the RT(1) signal is detected. 
When either of the WFG timer active flags is set, the WFG timer loads the initial value from the WFTM 
register and starts Down-count operation. After counting,
 it resets both of the WFG timer active flags to 0. 
Therefore, irrespective of the pulse width of the RT(0 ) and RT(1) signals, the WFG timer active flags are set 
for the cycle setting time of the WFG timer from the risi ng edge of each signal. During this period, the 
CH_PPG output can be superimposed on RTO. 
By the time this mode is selected by writing to th e WFSA register, each WFG timer active flag is already 
reset. When the mode is selected, the output of the RTO(0) and RTO(1) signals is set to the Low level, 
regardless of the output level of the RT(0) signal, RT(1) signal and CH_PPG signal. 
 
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 Figure 4-22  shows Example 2 of the operation waveform in Timer PPG mode of WFG-ch.10. 
Figure 4-22 Example 2 of Operation Waveform in WFG-Timer PPG Mode 
 
WFG wave form : Example2 of  Timer-PPG mode ( ch.10  WFSA10.GTEN=11, WFSA10.PGEN=11
RT0
CH10_PPG RTO0
CH10_GATE RT1
RTO1
WFG10 timer count
WFG timer active flag 0
WFG timer active flag 1
  
 
This figure shows an example of making the time setting of the WFG timer (WFTM) longer than the pulse 
length of RT0 and RT1. It indicates that although the same signals as in  Figure 4-21 are input for the RT0 
an d RT1 signal
s, th

e outputs that are different from the ones shown in  Figure 4-21 can be achieved because 
of the timer settin g

 time. 
Figure 4-23  shows Example 3 of the operation waveform in Timer PPG mode of WFG-ch.10.   
Figure 4-23 Example 3 of Operation Waveform in WFG-Timer PPG Mode 
 
WFG wave form : Example3 of Timer-PPG mo de ( ch.10 WFSA10.GTEN=11, WFSA10.PGEN=11)
RT0
CH10_PPG RTO0
CH10_GATE
RT1
RTO1
WFG10 timer count
WFG timer active flag 0
WFG timer active flag 1
▲  
 
This figure shows an exceptional case. The following operation is performed at the point indicated by 
▲ 
in the figure. WFG timer active flag0 is set at the  rising edge of the RT0 signal and WFG10 timer is in 
operation. In the meantime, the rising edge of the RT1  signal is detected and WFG timer active flag1 is set. 
In this case, WFG10 timer reloads the initial value an d performs the operation that will restart the timer 
count. Each WFG timer active flag is reset, when the counting by WFG10 timer is completed. For this 
reason, the period in which WFG tim er active flag0 is set becomes longer than the timer setting, as shown 
in the figure. Therefore, the output  of the waveform shown in the figure can be achieved for RTO0 and 
RTO 1 .  
 
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4. Registers of Multifunction Timer 
 
 RT Dead Timer Mode 
The operation in RT dead timer mode is as follows (see the List of Output Details). 
The output of the CH_GATE signal is always fixed to the Low level. 
As for the RTO(1) and RTO(0) sign als, the non-overlap signal that has the dead time set by WFG timer 
based on the RT(1) signal is output. 
In this mode, the RT(0) signal and the CH_PPG signal are not used. This mode assumes that the output 
polarity of OCU’s RT(1) output is Active High. The output polarity of RTO(0) and RTO(1) can be selected 
by WFSA.DMOD. 
Figure 4-24  shows Example 1 of the operation waveform in RT dead timer mode of WFG-ch.10. 
Figure 4-24 Example 1 of Operation Waveform in WFG-RT Dead Timer Mode 
 
WFG wave form : Example1 of RT-dead timer mode（  ch.10, Active High, WFSA10.DMOD=0)
RT1
RTO1
CH10_GATE(Low
）
RTO0
WFG10 tmer count
  
 
This figure shows an example of the case where  normal polarity (Active High) is selected by 
WFSA.DMOD=0. 
When the rising edge of the RT(1) is detected, the output of the RTO(1) signal is set to the Low level and 
WFG timer starts. Then, when the delay time by the WFG timer setting elapses, the RTO(0) signal is set to 
the High level. 
When the falling edge of the RT(1) is detected, the output of the RTO(0) signal is set to the Low level and 
WFG timer starts. Then, when the delay time by the WFG timer setting elapses, the RTO(1) signal is set to 
the High level. 
When this mode is selected by writing to the WFSA register, the RTO(0) signal is set to the same output 
level as for the RT(1) signal, while the RTO(1) signal is se t to the output level that is opposite from that of 
the RT(1) signal. 
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Figure 4-25 shows Example 2 of the operation waveform in RT dead timer mode of WFG-ch.10. 
Figure 4-25 Example 2 of Operation Waveform in WFG-RT Dead Timer Mode 
 
RT1
RTO1
CH10_GATE(Low)
RTO0
WFG10 timer count
WFG wave form : Example2 of RT-dead timer mode
（ ch.10, Active Low, WFSA10.DMOD=1)
  
 
This figure shows an example of the case where  reversed polarity (Active Low) is selected by 
WFSA.DMOD=1. 
When reversed polarity (Active Low) is specified, th e non-overlap signal is output with polarity reversed 
from the output level of the RTO(0) and RTO(1) signals. 
When this mode is selected by writing to the WFSA register, the RTO(0) signal is set to the output level that 
is opposite from that of the RT(1) signal and the RTO(1) signal is set to the same output level as for the 
RT(1) signal. 
Figure 4-26  shows Example 3 of the operation waveform in RT dead timer mode of WFG-ch.10. 
Figure 4-26 Example 3 of Operation Waveform in WFG-RT Dead Timer Mode 
 
WFG wave form : Example3 of RT-dead timer mode ( ch.10, Active High, WFSA10.DMOD=0 ）
RT1
RTO1
CH10_GATE(Low
）
RTO0
WFG10 timer count
  
 
This figure shows a case of normal pol arity (Active High). A pulse shorter than the dead time set by the 
WFTM register is input to the last RT1 signal in the fi gure. In this case, WFG10 timer starts counting at the 
rising edge of the RT1 signal and loads the initial value at the next falling edge to restart the operation. 
Therefore, no pulse will be output to RTO0. After the  falling edge of RT1, RTO1 is set to the High level 
when the timer setting time has elapsed. 
In the case of reversed polarity  (Active Low), no pulse is output to RTO(0), just like the above. 
 
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4. Registers of Multifunction Timer 
 
 PPG Dead Timer Mode 
The operation in PPG dead timer mode is as  follows (see the List of Output Details). 
The CH_GATE signal outputs the RT(1) signal, RT(0) signal or logic OR signal by GTEN[1:0] setting. 
As for the RTO(1) and RTO(0) sign als, the non-overlap signal that has the dead time set by WFG timer 
based on the CH_PPG signal is output. 
In this mode, the RT(0) and RT(1) signals are used only for the output of the CH_GATE signal. 
Figure 4-27  shows Example 1 of the operation waveform in PPG dead timer mode of WFG-ch.10. 
Figure 4-27 Example 1 of Operation Waveform in WFG-PPG Dead Timer Mode 
 
WFG wave form : Example1 PPG-dead timer mode  （ ch.10, Active High WFSA10.GTEN=00, WFSA.DMOD=0)
CH10_PPG
RTO0
CH10_GATE
RTO1
WFG10 timer count
  
 
This figure shows an example of the case where  WFSA.DMOD=0 and normal polarity (Active High) are 
selected. As shown in the figure, the WFG timer starts at the rising and falling edges of the CH_PPG signal 
and the non-overlap signal with the delay time set by the WFTM applied to the RT O(0) and RTO(1) signals 
is output. 
When this mode is selected by writing to the WFSA register, the RTO(0) signal is set to the same output 
level as for the CH_PPG signal and the RTO(1) signal is  output at the output level that is opposite from that 
of the CH_PPG signal. 
Figure 4-28  shows Example 2 of the operation waveform in PPG dead timer mode of WFG-ch.10. 
Figure 4-28 Example 2 of Operation Waveform in WFG-PPG Dead Timer Mode 
 
WFG wave from : Exampl e2 PPG-dead timer mode  （ ch.10, Active Low, WFSA10.GTEN=00, WFSA10.DMOD= １）
CH10_PPG
RTO0
CH10_GATE
RTO1
WFG10 timer count
  
 
This figure shows an example of the case where WF SA.DMOD=1 and reversed polarity (Activator) are 
selected. As shown in the figure, the non-overlap signal with the output level reversed from that of the 
RTO(0) and RTO(1) signals is output. 
When this mode is selected by writing to the WFSA register, the RTO(0) signal is set to the output level that 
is opposite from that of the CH_PPG signal and the RT O(1) signal is output at the same output level as for 
the CH_PPG signal. 
If the pulse width of the CH_PPG signal is shorter th an the WFG timer, no pulse will be output to RTO(0), 
just like the case in  Figure 4-26. 
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CHAPTER  15: Multifunction  Timer 
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