Fujitsu Series 3 Manual
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FUJITSU SEMICONDUCTOR LIMITED When receive FIFO is enabled: 1. If NACK is detected, the interrupt flag (IBCR:INT) is set to 1, and the I2C bus is placed into the wait state. When receive FI FO becomes full, place the I2C bus into the wait state. If the stop or iteration start condition is detected, the IBSR:SPC and IBSR:RSC bits are set to 1, and the interrupt flag (IBCR:INT) is not set to 1 (the I 2C bus is not placed into the wait state). Receive FIFO sets the SSR:RDRF bit to 1 when the set value of the FBYTE register matches the number of data sets received. If the SMR:RIE bit is then 1 , a receive interrupt is generated. 2. When the interrupt flag (IBCR:INT) is set to 1, read the received data from the RDR register. After all data has been read, write 0 to the interrupt flag to release the wait state of the I2C bus. When receive FIFO is full, release the wait state of the I2C bus if the received data is read from the RDR register even once. If the stop or iteration start condition is detected, read all the received data from the RDR register, and clear the IBSR :SPC or IBSR:RSC bit to 0. Figure 2-39 Slave mode receive interrupt 1 by disabling FIFO (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=0) S Slave Address ACK Data W DataACKDataACK P or SrNACK Figure 2-40 Slave mode receive interrupt 2 by disabling FIFO (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0) : Interrupt by INTE =1 : Interrupt by CNDE = 1 As the slave address matches , an ACK is output and an interrupt is generated . - ACKE bit is set to 1 and INT bit is set to 0 . An interrupt occurs when a single byte is received and an ACK is responded . -After the received data has been read from the receive buffer, the INT bit is set to 0 . An interrupt occurs when a single byte is received and a NACK is responded . -After the received data has been read from the receive buffer, the INT bit is set to 0 . S Slave Address ACK Data ACK W DataACKDataACK P or Sr : Interrupt by INTE =1 : Interrupt by CNDE = 1 As the slave address matches , an ACK is output and an interrupt is generated . - ACKE bit is set to 1 and INT bit is set to 0 . An interrupt occurs when a single byte is received . -After the received data has been read from the receive buffer, the INT bit is set to 0 . An interrupt occurs when a single byte is received . -After the received data has been read from the receive buffer, the INT bit is set to 0 . CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1005 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Figure 2-41 Slave mode receive interrupt 3 by disabling FIFO (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0) S Slave Address ACK Data W DataACKDataACK P or SrNACK Figure 2-42 Slave mode receive interr upt 4 by enabling receive FIFO (SSR:DMA=0, IBSR:RSA=0) Figure 2-43 Slave mode receive interr upt 5 by enabling receive FIFO (SSR:DMA=0, IBSR:RSA=0) : Interrupt by INTE =1 : Interrupt by CNDE = 1 As the slave address matches , an ACK is output and an interrupt is generated . - ACKE bit is set to 1 and INT bit is set to 0 . An interrupt occurs when a single byte is received . -After the received data has been read from the receive buffer, the INT bit is set to 0 . An interrupt occurs when a NACK is responded . -INT bi t is se t to 0. S ACK Data ACK Slave Address WDataACKDataACK P or Sr : Interrupt by INTE =1 : Interrupt by CNDE = 1 An interrupt occurs when the stop condition or the iteration start condition is detected . -The entire data is read from the Receive FIFO buffer. S ACK Data ACK Slave Address WDataACKDataACK P or Sr : Interrupt by INTE =1 : Interrupt by CNDE = 1 An interrupt occurs when the Receiv e FIFO buffer is filled with data. 0 . -The entire data is read f r om the Receive FIFO buffe r, and the INT bit is set to CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1006 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Figure 2-44 Slave mode receive interrupt 6 by disabling FIFO (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=1) S Slave Address ACK Data ACK W DataACKDataACK P or Sr Figure 2-45 Slave mode receive interrupt 7 by disabling FIFO (SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=0) : Interrupt by INTE =1 : Interrupt by CNDE = 1 : Interrupt by RIE =1 As the slave address matches , an ACK is output and an interrupt is generated . - ACKE bit is set to 1 and INT bit is set to 0 . An interrupt occurs ( but the I 2C bus is not waited) when a single byte is received . -The received data is read from the receive buffer. The I2C bus is waited when an ACK is responded . -The received data is read from the receive buffe r. An interrupt occurs when a single byte is received and a NACK is responded . - After the received data has been read from the receive buffer, the INT bit is set to 0 . Slave Address S WACK DataACK DataACKData NACKP or Sr : Interrupt by INTE =1 : Interrupt by CNDE = 1 . An interrupt occurs as the reserved address (0000 xxxx or 1111 xxxx) matches The received data is read - , and ACKE bit is set to 1 and INT bit is set t o 0 . An interrupt occurs when a single byte is received and an ACK is output . -INT bit is se t to 0. An interrupt occurs when a single byte is received and an ACK is output . An interrupt occurs if INT bit is set to 0 . - CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1007 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Figure 2-46 Slave mode receive interrupt 8 by disabling FIFO (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0) S ACK Data ACK W DataACKDataACK P or SrSlave Address Figure 2-47 Slave mode receive interrupt 9 by disabling FIFO (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0) : Interrupt by INTE= 1 : Interrupt by CNDE= 1 : Interrupt by RIE =1 As the slave address matches , an ACK is output and an interrupt is generated . - ACKE bit is set to 1 and INT bit is set to 0 . An interrupt occurs when a single byte is received . - The received data is read from the receive buffer. An interrupt occurs when a single byte is received. - The received data is read from the receive buffer. S ACK Data WDataACKDataACK P or SrSlave AddressNACK : Interrupt by INTE= 1 : Interrupt by CNDE= 1 : Interrupt by RIE =1 As the slave address matches , an ACK is output and an interrupt is generated . - ACKE bit is set to 1 and INT bit is set to 0 . An interrupt occurs when a single byte is received . - The received data is read from the receive buffer. An interrupt occurs when a NACK is responded. - INT bit is set to 0. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1008 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Figure 2-48 Slave mode receive interrupt 10 by enabling receive FIFO (SSR:DMA=1, IBSR:RSA=0) S ACK Data ACK W DataACKDataACK P or SrSlave Address Figure 2-49 Slave mode receive interrupt 11 by enabling receive FIFO (SSR:DMA=1, IBSR:RSA=0) Figure 2-50 Slave mode receive interrupt 12 by disabling FIFO (SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=1) : Interrupt by INTE =1 : Interrupt by CNDE = 1 An interrupt occurs when the stop condition or the iteration start condition is detected . -The entire data is read from the Receive FIFO buffer. S ACK Data ACK W DataACKDataACK P or SrSlave Ad dress : Interrupt by CNDE = 1 As the Receive FIFO buffer is filled with data , the IC bus is waited .2 The waiti ng is released when data is read even once from the Receive FIFO buffe r . - An interrupt occurs when the stop condition or the iteration start condition is detected . - The entire data is read from the Receive FIFO buffer. S ACK Data ACK Slave Address WDataACKDataACK P or Sr : Interrupt by INTE= 1 : Interrupt by CNDE= 1 : Interrupt by RIE =1 An interrupt occurs as the reserved address (0000 xxxx or 1111 xxxx) matches . - , The received data is read and ACKE bit is set to1 and INT bit is set to 0 . An interrupt occurs when a single byte is received and an ACK is output . - . The received data is read An interrupt occurs when a single byte is received and an ACK is output . - . The received data is read CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1009 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Transmission in slave mode If the received data matches the slave address and the data direction bit is 1, it means that data is transmitted in slave mode. If FIFO is disabled, set the interrupt flag (IBCR:INT) to 1 after transmitting one byte or outputting an acknowledgement response depending on setting of the IBCR:WSEL bit. Then place the I 2C bus into the wait state (see Ta b l e 2 - 8). Using the IB SR:RACK bit, check the acknowledgement output from the master device. If NACK response is returned from the master device, it means that the master device could not receive data correctly or data receiving was ended. If NACK is detected at IBCR: WSEL=1, an interrupt is generated to place the I 2C bus into the wait sate. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1010 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 2.4. Bus error If the stop or (iteration) start condition is detected while transmitting or receiving data on the I2C bus, it is handled as a bus error. Bus error occurrence condition If a bus error occurs, the IBCR:BER bit is set to 1 in the following conditions. The (iteration) start or stop condition is detected while transferring the first byte. The (iteration) start condition or stop condition is de tected at bit 2 to 9 (acknowledgement) of data. Bus error operation If the interrupt flag (IBCR:INT) is set to 1 by transmitting or receiving data, check the IBCR:BER bit. When the IBCR:BER bit is 1, perform error processing. The IBCR:BER bit is cleared by writing 0 to the IBCR:INT bit. If a bus error occurs, the IBCR:INT bit is set to 1; however, the I 2C bus is not placed into the wait state by setting its SCL to LOW. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1011 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 3. Dedicated Baud Rate Generator The dedicated baud rate generator configures the setting of the serial clock frequency. Selecting the baud rate Baud rate obtained by dividing an internal clock using the dedicated baud rate generator (reload counter) This generator provides two internal reload counters, which support transmitting and receiving serial clocks respectively. To select the baud rate, specify the 15-bit reload value using Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). Each reload counter divides an internal clock by the set value. Calculating the baud rate Two 15-bit reload counters are set using the Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). The baud rate is obtained in the following formulas. (1) Reload value V = / b - 1 V: Reload value b: Baud rate : Bus clock frequency or external clock frequency Note that the preset baud rate may not be generated at a rising edge of signal on I 2C bus. In such case, adjust the reload value. (2) Calculation exam ple To set the 16MHz bus block and 400K-bps baud rate, set the reload value as follows. Reload value:V = (16 x 1000000)/400000 - 1 = 39 Therefore, the baud rate is: b = (16 x 1000000)/(38 + 2) = 400kbps Write Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) by 16-bit access operation. When the ISMK:EN bit in the ISMK register is 0, set the value of each Baud Rate Generator Register. In operation mode 4 (I2C mode), operate the bus clock at a frequency no lower than 8 MHz. Also note that setting of a baud rate generator that exceeds 400 kbps is prohibited. If the reload value is set to 0, the reload counter is stopped. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1012 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Reload values and baud rates for each bus clock frequency Table 3-1 Reload values and baud rates 8 MHz 10 MHz 16 MHz 20 MHz 24 MHz 32MHz Baud rate [bps] Value Value Value Value Value Value 400000 19 24 39 49 59 79 200000 39 49 79 99 119 159 100000 79 99 159 199 239 319 The numeric values above are available when the SCL rising timing of the I2C bus is 0s. If the SCL rising timing of the I2C bus is late, the baud rate is set to the value later than the numeric values above. Functions of reload counter Each reload counter consists of a 15-bit register for the reload value, and generates transmitting and receiving clocks from internal cloc ks. The count value of the transmit re load counter can be read from the Baud Rate Generator Registers (BGR1 and BGR0). Starting counting When the reload value is written to the Baud Rate Ge nerator Register (BGR1 or BGR0), the reload counter starts counting. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1013 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 4. I2C communication operation flowchart examples This section shows I2C communication operation flowchart examples. I2C flowchart example (FIFO not used) when DMA mode is disabled (SSR:DMA=0) Figure 4-1 I2C flowchart example (FIFO not used) when DMA mode is disabled (SSR:DMA=0) 1/3 Start Initial settings: Baud rate (BGR) Slave address (ISBA) Slave mask (ISMK) I 2C enabling (ISMK:EN=1) Master mode? Write the send data. (TDR)Set the Master mode. (IBCR:MSS=1) IBCR:INT=1 ? IBCR:BER=0 ? IBCR:ACT=1 ? Yes Yes Yes IBCR:MSS=1 ? Yes IBSR:RSA=0 ? Yes IBSR:RACK=0 ? IBSR:TRX=1 ? Write the send data. (TDR) Set the waiting. (IBCR:WSEL) Set an ACK. (IBCR:ACKE) Clear the interrupt flag. (IBCR:INT=0) Completed to send? Start to iterate? Write the send data. (TDR)Set the iteration start. (IBCR:MSS=SCC=1)Set an ACK. (IBCR:ACKE) Clear the interrupt flag. (IBCR:INT=0) Set to stop. (IBCR:MSS=0) Set an ACK. (IBCR:ACKE) Clear the interrupt flag. (IBCR:INT=0) End IBSR:FBT=0? Read the received data. (RDR) Completed to receive? Set the waiting. (IBCR:WSEL=1) Set an ACK. (IBCR:ACKE=1) Clear the interrupt flag. (IBCR:INT=0) Reserved address Slave mode Arbitration Lost processing End Bus error processing No No No No No No No No No Yes Yes Yes Yes Yes No No Yes (NACK response) No Yes A B Set the waiting. (IBCR:WSEL) Set an ACK. (IBCR:ACKE=0) CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1014 MB9Axxx/MB9Bxxx Series