Fujitsu Series 3 Manual

							 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.8.  FIFO Control Register 0 (FCR0) 
The FIFO Control Register 0 (FCR0) is used to enable/disable the FIFO operation, reset FIFO, 
save the read pointer, and set the data re-transmission. 
 
Bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (FCR1) - FLSTFLD FSETFCL2FCL1 FE2 FE1 
Attribute      -  R R/W  R/W R/W R/W  R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] Reserved bit  0 is always read during reading. 
0 must always be written during writing. 
 
[bit 6] FLST: FIFO re-transmit data lost flag bit  This bit shows that the re-transmit data of transmit FIFO has been lost. 
The FLST bit is set when: 
  The FLSTE bit of FIFO Control Register 1 (FCR1) is 1, the write pointer of transmit FIFO matches the 
read pointer which has been saved by th e FSET bit, and data is written in FIFO. 
 
The FLST bit is reset when: 
   FIFO is reset (FCL bit is set to 1). 
   The FSET bit is set to 1. 
 
If this bit is set to 1, the data identified by the  read pointer (saved by the FSET bit) is overwritten. 
Therefore, the FLD bit cannot set the data re-transmission even if an error has occurr ed. If this bit is set to 
1 and if you wish to re-transmit data, first reset FIFO. Then, write data in the FIFO buffer again. 
Bit Description 
0  No Data Lost has occurred. 
1  Data Lost has occurred. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 5] FLD: FIFO pointer reload bit 
This bit reloads the data, being saved in transmit FIFO by  the FSET bit, to the reload pointer. This bit can be 
used to re-transmit data after a communication error or others have occurred. 
When the re-transmission setting has finished, this bit is set to 0. 
Bit Description 
0 Not  reloaded 
1 Reloaded 
 
 
  If th is 

bit is 1, data is being reloaded in the read  poin
 ter. Therefore, data writing except for FIFO reset 
is disabled. 
   When FIFO is enabled or when data is being transmitted, this bit cannot be set to 1. 
   After you have set the SCR:TIE bit and SCR:TBIE bit to  0, set this bit to 1. After you have enabled 
transmit FIFO, set the SCR:TIE bit and SCR:TBIE bit to 1. 
 
[bit 4] FSET: FIFO pointer save bit  This bit save s th

e transmit FIFO read pointer. 
If the read pointer is saved before transmission and if  the FLST bit is 0, data can be re-transmitted even 
when a communication error or others occur. 
If set to 1: The current read pointer value is saved. 
If set to 0: No effect. 
Description Bit  During writing During reading 
0 Not  saved 
1 Saved  0 is always read. 
 
 
This  b

it can be set to 1 only when the transmit byte count (FBYTE) is 0. 
 [bit 3] FCL2: FIFO2 reset bit  This bit resets th e FIFO2 value. 
Wh

en this bit is set to 1, the FIFO2 internal state is initialized. 
Only the FCR1:FLST2 bit is initialized, but the other bits of FCR1/0 registers are kept. 
Description Bit  During writing During reading 
0 No  effect. 
1 FIFO2 is reset.  0 is always read. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
 
  Disable the transmission and receptio n first, and then reset FIFO2. 
   Set the tran

smit FIFO interrupt enable bit to 0 before the execution. 
   The valid data count of the FBYTE2 register is set to 0. 
 
[bit 2] FCL1: FIFO1 reset bit  This bit resets th e FIFO1 state. 
Wh

en this bit is set to 1, the FIFO1 internal state is initialized. 
Only the FCR1:FLST1 bit is initialized, but the other bits of FCR1/0 registers are kept. 
Description Bit  During writing During reading 
0 No  effect. 
1 FIFO1 is reset.  0 is always read. 
 
 
  Disable th e tra

nsmission and receptio n first, and then reset FIFO1. 
   Set th e tran

smit FIFO interrupt enable bit to 0 before the execution. 
   The valid data count of the FBYTE1 register is set to 0. 
 
[bit 1] FE2: FIFO2 operation enable bit  This bit  ena

bles or disables the FIFO2 operation. 
   To use the FIFO2 operation,  set this bit to 1. 
   If FIFO2 is set as transmit FIFO (FCR1:FSEL=1) and if  data exists in FIFO2 when this bit is set to 1, 
the data transmission starts immediately when th e UART is enabled to transmit data (SCR:TXE=1). 
During this time, set both SCR:TIE bit and SCR:TBIE bit to 0. Then, set this bit to 1 and set both 
SCR:TIE bit and SCR:TBIE bit to 1. 
   If receive FIFO is selected by the FSEL bit and if a r eceive error has occurred, this bit is cleared to 0. 
This bit cannot be set to 1 un til the receive error is cleared. 
   If FIFO2 is used as transmit FIFO, this bit must be  set to 1 or 0 when the transmit buffer is empty 
(SSR:TDRE=1). 
   If FIFO2 is used as receive FIFO, this bit must  be set to 0 when the receive buffer is empty 
(SSR:RDRF=0) and no valid data exists in receive  FIFO (FBYTE2=0) after reception is disabled 
(SCR:RXE=0). 
   If FIFO2 is used as receive FIFO, this bit must  be set to 1 when the receive buffer is empty 
(SSR:RDRF=0) after receptio n is disabled (SCR:RXE=0). 
   The FIFO2 state is held even if the FIFO2 operation is disabled. 
 
Bit Description 
0  Disables the FIFO2 operation. 
1  Enables the FIFO2 operation. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 0] FE1: FIFO1 operation enable bit 
This bit enables or disables the FIFO1 operation. 
  To use the FIFO1 operation,  set this bit to 1. 
   If FIFO1 is set as transmit FIFO (FCR1:FSEL=0) and if  data exists in FIFO1 when this bit is set to 1, 
the data transmission starts immediately when th e UART is enabled to transmit data (SCR:TXE=1). 
During this time, set both SCR:TIE bit and SCR:TBIE bit to 0. Then, set this bit to 1 and set both 
TIE bit and TBIE bit to 1. 
   If receive FIFO is selected by the FSEL bit and if a r eceive error has occurred, this bit is cleared to 0. 
This bit cannot be set to 1 un til the receive error is cleared. 
   If FIFO1 is used as transmit FIFO, this bit must be  set to 1 or 0 when the transmit buffer is empty 
(SSR:TDRE=1). 
   If FIFO1 is used as receive FIFO, this bit must  be set to 0 when the receive buffer is empty 
(SSR:RDRF=0) and no valid data exists in receive  FIFO (FBYTE2=0) after reception is disabled 
(SCR:RXE=0). 
   If FIFO1 is used as receive FIFO, this bit must  be set to 1 when the receive buffer is empty 
(SSR:RDRF=0) after receptio n is disabled (SCR:RXE=0). 
   The FIFO1 state is held even if the FIFO1 operation is disabled. 
 
Bit Description 
0  Disables the FIFO1 operation. 
1  Enables the FIFO1 operation. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
5.9.  FIFO Byte Register (FBYTE) 
The FIFO Byte Register (FBYTE) indicates the effective data count in the FIFO buffer. 
 
Bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field (FBYTE2) (FBYTE1) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
The FBYTE register indicates the effective data coun t of FIFO. The following shows the settings of the 
FCR1:FSEL bit. 
Table 5-3 Display of data count 
FSEL FIFO selection Byte count display 
0  FIFO2: Receive FIFO, FI FO1: Transmit FIFO  FIFO2:FBYTE2, FIFO1:FBYTE1 
1  FIFO2: Transmit FIFO, FIFO1: Receive FIFO  FIFO2:FBYTE2, FIFO1:FBYTE1 
 
  The initial value of data transfer coun t is 0x08 for the FBYTE register. 
   Set a data count to flag a receive interrupt for the FBYTE register of receive FIFO. If  this transfer data 
count matches the FBYTE register display, the interrupt flag (SSR:RDRF) is set to 1. 
   If both conditions below are satisfied  and if the receive idle state continues for more than 8 baud rate 
clocks, the interrupt flag (RDRF) is set to 1. 
  The receive FIFO idle detection enable bit (FRIIE) is 1. 
   The number of data sets stored in the recei ve FIFO does not reach the transfer count. 
If the RDR data is read during counting of 8 clocks, this counter is reset to 0, and counting for 8 clocks 
is restarted. If receive FIFO is disabled, this counter  is reset to 0.If data remains in the receive FIFO 
and if receive FIFO is enabled,  the data counting is restarted. 
   To receive data in the master mode operation (mas ter mode reception), set both SCR:TIE and SCR:TBIE 
bits to 0, set the receive data count in the FB YTE register of transmit FIFO, and set the FCR1:FDRQ 
bit to 0. After that, when the SCR:TXE bit is 1, the serial clock is output for the preset data amount, 
and the preset amount of data can be received. Set  the SCR:TIE bit and SCR:TBIE bit to 1 only after 
the FCR1:FDRQ bit has been set to 1. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
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Chapter: CSIO (Clock Sync Serial Interface) 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  59  
FBYTE2, FBYTE1: FIFO2 data count display bit, FIFO1 data count display bit 
During writing Sets the transfer data count. 
During reading Reads the effective count of data. 
 
Read (Effective data count) 
During transmission: The number of data sets  already written in FIFO but not transmitted yet 
During reception: The number of  data sets received in FIFO 
Write (Transfer data count)  During transmission: Set 0x00. 
During reception: Set the data count  to generate a receive interrupt. 
 
   The FBYTE register of transmit FIFO must be 8h00 except when data is received in the master mode 
operation. 
   During the master mode data reception, the transmit da ta count must be set only when transmit FIFO is 
empty and both SCR:TIE bit and SSR:TBIE bit are 0. 
   To disable the reception (SCR:RXE=0) when data is  being received in the master mode operation, 
disable transmit FIFO first, and then disable the transmission and reception. 
   The FBYTE bit of receive FIFO must be set to 1 or larger. 
   Change the FBYTE data of receive FIFO only after you have disabled the data reception. 
   A read-modify-write instruction cannot be used for this register. 
   Any setting exceeding the FIFO  capacity is inhibited. 
   When all the following requirements  are met, the receive data full flag bit (SSR:RDRF) is not set to 1 
even though the effective data of  FBYTE setting number exist in the r eceive FIFO. If the FBYTE register 
is set to 2 or greater, this operation will not occur. 
  FBYTE is set to 1. 
   The effective data count is 1, same as  the number specified in FBYTE register. 
   When the multi function serial interface macro r eceives the data, and writes received data in the 
reception FIFO, the data of the receptio n FIFO are read at the same time.   
However, after that, the receive data full flag bit (S SR:RDRF) will be set to 1 at any of the following 
conditions. 
  The next data is received. 
   The receive idele state of 8 bits  or longer is detected when the receive FIFO idele is enabled 
(FCR:FRIIE=1)  
 
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							 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: LIN Interface (Ver. 2.1) (LIN Communication Control Interface Ver. 2.1) 
This chapter explains the LIN communication function, a part of multifunctional serial interface 
functions and supported in Operation Mode 3. 
 
1.
 Overview of LIN Interface (Ver. 2.1) (LIN Communication Control Interface Ver. 2.1) 
2. LIN Interface (Ver.  2.1) Interrupts 
3. Dedicated Baud Rate Generator 
4. LIN Interface (Ver. 2.1) Operations 
5. Operation Mode 3 (LIN Communication Mode) Setting Procedure and Program Flow 
6. LIN Interface (ver. 2.1) Registers 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FM15L-E05.2 
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							 FUJITSU SEMICONDUCTOR LIMITED 
1.  Overview of LIN Interface (Ver. 2.1) (LIN Communication Control Interface Ver. 2.1) 
The LIN interface (ver. 2.1) (LIN communication control interface ver. 2.1) supports functions 
complying with the LIN bus. It also has transmit/receive FIFO (up to 128 × 9 bits each)*1 
installed. 
 Functions of LIN interface (ver. 2.1) (L IN communication control interface ver. 
2.1) 
 
   Function 
1 Data buffer 
  Full duplex double buffer (when FIFO is not used) 
   Transmit/receive FIFO (max  128 × 9 bits each) *1 (when FIFO is used) 
2 Serial input  Run oversampling three times with th
e bus clock and determine the value 
of received data based on th e majority sampling value. 
3 Transfer mode  Asynchronous 
4 Baud rate 
  Complete with a dedicated baud rate generator (constructed with a 
15-bit reload counter) 
   The external clock can be adjust ed with the reload counter. 
5 Data length  8 bits 
6 Signaling system  NRZ (Non Return to Zero) 
7 Start bit detection  Synchronized with the falling edge of the start bit 
8 Receive error detection 
  Framing error 
   Overrun error 
9 Interrupt request  
  Receive interrupts   
(reception completed, framing error, overrun error) 
   Transmit interrupts (transmit data empty, transmit bus idle) 
   Status interrupts (LIN break field detection) 
   Interrupt request to ICU (LIN Sync field detection: LSYN) 
   Transmit FIFO interrupt (when transmit FIFO is empty) 
   For both transmission and reception, the extended intelligent I/O 
service (EIIOS) and the DM A function are available. 
10 LIN bus option 
  Supports LIN Protocol Revision 2.1 
   Master device operations 
   Slave device operations 
   LIN break field generation (with variable bit length ranging from 13 to 
16 bits) 
   LIN break delimiter generation (with variable data length ranging from 
1 to 4 bits) 
   LIN break field detection 
   Detection of LIN sync field start/stop edges connected to input capture 
11 FIFO options  
  Transmit/receive FIFO installed (maximum capacity: 128 × 9 bits for 
transmit FIFO, 128 × 9 b its for receive FIFO) 
*1  
   Transmit FIFO or receive FIFO can be selected. 
   Transmit data can be resent. 
   Receive FIFO interrupt timing  can be changed via software. 
   FIFO resetting is supported independently. 
*1: The FIFO capacity size varies from model type to model type. 
 
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2. LIN Interface (Ver. 2.1) Interrupts 
 
2.  LIN Interface (Ver. 2.1) Interrupts 
Receive interrupts and transmit interrupts are provided for LIN interface (ver. 2.1). These 
interrupt requests can be generated if: 
- Incoming data is set in the Receive Data Register (RDR) or a data receive error occurs. 
- Outgoing data is transferred from the Transmit Data Register (TDR) to the transmit shift 
register and the data transmission is started. 
- The transmit bus is idle (No data transmission occurs). 
- Transmit FIFO data is requested. 
- A LIN break field is detected 
  LIN interface (ver. 2.1) interrupts 
Ta b l e  2 - 1  shows the interrupt control bits and the interrupt causes of LIN interface (ver. 2.1). 
Table 2-1 LIN interface (ver. 2.1) interrupt control bits and interrupt causes 
Interrupt  
type  Interrupt 
request flag bit  Flag  
register  Interrupt cause  Interrupt 
cause 
enable bit Operation to clear   
interrupt request flag 
A single-byte reception Reading from the received data register (RDR) 
Reception of a data 
volume matching the 
value set for FBYTE. 
RDRF SSR While the FRIIE bit is 
1 and the receive 
FIFO contains valid 
data, a receive idle state 
continues for 8 bits or 
longer period.  Reading from the Received Data Register (RDR) 
until receive FIFO is emptied 
ORE SSR 
Overrun error 
Reception 
FRE SSR Framing error  SCR:RIE 
Setting the Reception Error Flag Clear bit 
(SSR:REC) to 1   
TDRE SSR  The Transmit Data 
Register is empty  SCR:TIE Writing to the Transmit Data Register (TDR) or 
setting the transmit FIFO operation enable bit to 
1 when the transmit FIFO operation enable bit 
is set to 0 and valid data are present in transmit 
FIFO (re-transmitting data) 
*1 
TBI 
SSR No data transmission  SCR:TBIEWriting to the Transmit Data Register (TDR), 
setting the LIN break field setting bit (LBR) to 
1, or setting the transmit FIFO operation 
enable bit to 1 when the transmit FIFO 
operation enable bit is set to 0 and valid data 
are present in transmit FIFO (re-transmitting 
data).
*1 
Transmission 
FDRQ FCR1  Transmit FIFO is 
empty.  FCR1:FTIEThe FIFO transmit data request bit (FCR1:FDRQ) 
is set to 0 or transmit FIFO is full. 
Status LBD 
SSR LIN break field is 
detected  ESCR:LBIE
The SSR:LBD bit is set to 0. 
ICP0 ICS0  The first rising edge in 
the LIN Sync field 
Input capture 
ICP0 ICS0  The fifth falling edge in 
the LIN Sync field  ICS0:ICE0
Disables ICP0 
*1: Set the TIE bit to 1 only after the TDRE bit has been set to 0. 
 
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2. LIN Interface (Ver. 2.1) Interrupts 
 
2.1.  Receive interrupt and flag set timing 
Data reception can be interrupted by a receive completion (SSR:RDRF), a receive error 
occurrence (SSR:ORE, FRE), or a LIN break field detection. 
  Receive interrupt and flag set timing   
Upon detection of the first  stop bit, received data are stored in the Receive Data Register (RDR). When the 
data reception is completed (SSR:RDRF = 1) or when  a data receive error occurs (SSR:ORE, FRE = 1), 
each flag is set. If receive interrupts are enabled (SSR:R IE = 1) during this time, a receive interrupt occurs. 
 
If a recei ve e

rror occurs, data in the Receive Data Register (RDR) is invalidated. 
 
Figure 2-1 RDRF (Receive Data Register Full) flag bit set timing 
 
Receive data
RDRF ST D0 D1 D2  
D5 
D6 D7 SP ST
A receive interrupt occurred.
  
 
Figure 2-2 FRE (Framing Error) flag bit set timing 
 
Receive data
RDRF
Precautions: - When the first stop bit is at LOW level, a framing error occurs.
- The RDRF bit is set to 1 and data can be received even if a framing error has occurred. However, the receive data is invalid.
ST D0 D1 D2 D5 D6 D7
SP ST
A receive interrupt occurred.
FRE
  
 
  During recepti on, if a falling 

edge of the serial data is detected conc urrentl
 y with, or 1 to 2 bus clocks 
before the sampling po int of the stop bit, the edge is ignored and the next data may not be received 
successfully. To output frames continuously, ade quate intervals are required between frames. 
 
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