Fujitsu Series 3 Manual
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6. Registers
6.9. Hardware Watchdog Timer Control Register (WDG_CTL)
WDG_CTL register sets enable/disable of the hardware watchdog timer.
Register configuration
bit 7 2 1 0
Field Reserved RESEN INTEN
Attribute - R/W R/W
Initial value - 1’b1 1’b1
Register function
[bit7:2] res : Reserved bits
0b000000 is read from these bits.
In case of writing, set these bits to 0b000000.
[bit1] RESEN : Hardware wa tchdog timer reset enable bit
bit Explanation
In case of reading A...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-375.png "Page 376
6. Registers
6.9. Hardware Watchdog Timer Control Register (WDG_CTL)
WDG_CTL register sets enable/disable of the hardware watchdog timer.
Register configuration
bit 7 2 1 0
Field Reserved RESEN INTEN
Attribute - R/W R/W
Initial value - 1’b1 1’b1
Register function
[bit7:2] res : Reserved bits
0b000000 is read from these bits.
In case of writing, set these bits to 0b000000.
[bit1] RESEN : Hardware wa tchdog timer reset enable bit
bit Explanation
In case of reading A...")
![Page 377
6. Registers
6.10. Hardware Watchdog Timer Clear Register (WDG_ICL)
WDG_ICL register clears the hardware watchdog timer.
Register configuration
bit 7 0
Field WDG_ICL
Attribute R/W
Initial value 0xxx
Register function
[bit7:0] WDG_ICL : clear bit
bit7:0 Explanation
In case of reading Undefined value is read.
In case of writing Writing an arbitrary 8-bit value, and then write a reversal value of the
arbitrary value,
Clears an interrupt, if an interrupt of watchdog...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-376.png "Page 377
6. Registers
6.10. Hardware Watchdog Timer Clear Register (WDG_ICL)
WDG_ICL register clears the hardware watchdog timer.
Register configuration
bit 7 0
Field WDG_ICL
Attribute R/W
Initial value 0xxx
Register function
[bit7:0] WDG_ICL : clear bit
bit7:0 Explanation
In case of reading Undefined value is read.
In case of writing Writing an arbitrary 8-bit value, and then write a reversal value of the
arbitrary value,
Clears an interrupt, if an interrupt of watchdog...")
![Page 378
6. Registers
6.11. Hardware Watchdog Timer Interrupt Status Register (WDG_RIS)
WDG_RIS register shows the status of the hardware watchdog timer.
Register configuration
bit 7 1 0
Field Reserved RIS
Attribute - R
Initial value - 1’b0
Register function
[bit7:1] res : Reserved bits
0b0000000 is read from these bits.
In case of writing, set 0b0000000.
[bit0] RIS : Hardware watchdog interrupt status bit
bit Explanation
In case of writing No effect
In case of reading 0...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-377.png "Page 378
6. Registers
6.11. Hardware Watchdog Timer Interrupt Status Register (WDG_RIS)
WDG_RIS register shows the status of the hardware watchdog timer.
Register configuration
bit 7 1 0
Field Reserved RIS
Attribute - R
Initial value - 1’b0
Register function
[bit7:1] res : Reserved bits
0b0000000 is read from these bits.
In case of writing, set 0b0000000.
[bit0] RIS : Hardware watchdog interrupt status bit
bit Explanation
In case of writing No effect
In case of reading 0...")
![Page 379
6. Registers
6.12. Hardware Watchdog Timer Lock Register (WDG_LCK)
WDG_LCK register controls all the registers of the hardware watchdog timer.
Register configuration
bit 31 0
Field WDG_LCK
Attribute R/W
Initial value 0x00000001
Register function
[bit31:0] WDG_LCK : Hardware watchdog lock register
bit31:0 Explanation
In case of writing In case of writing 0x1ACCE551:
The locks of all the registers other than the control register are released.
Later, in...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-378.png "Page 379
6. Registers
6.12. Hardware Watchdog Timer Lock Register (WDG_LCK)
WDG_LCK register controls all the registers of the hardware watchdog timer.
Register configuration
bit 31 0
Field WDG_LCK
Attribute R/W
Initial value 0x00000001
Register function
[bit31:0] WDG_LCK : Hardware watchdog lock register
bit31:0 Explanation
In case of writing In case of writing 0x1ACCE551:
The locks of all the registers other than the control register are released.
Later, in...")
1. Overview CHAPTER: Dual Timer This chapter introduces the Dual Timer functions and operations. 1. Overview 2. Architecture 3. Operation Description 4. Setting Procedure Example 5. Register CODE: 9BFDT-E01.1_SP804-E01.0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 345 MB9Axxx/MB9Bxxx Series
1. Overview 1. Overview Dual Timer consists of two programmable 32/16-bit down counters. An interrupt is generated when the count reaches zero. Dual Timer Overview Dual Timer consists of two programmable Free Running Counters. Each timer block operates identically. The Free Running Counters can be programmed for 32-bit or 16-bit counter size by Control Register. Also, any one of the following three timer modes can be selected: Free-running mode The counter operates continuously and wraps around to its maximum value each time that it reaches zero. Periodic mode The counter is reloaded from Load Register and op erates continuously each time that it reaches zero. One-shot mode Writing to the Load Register loads the counter with a new value. The counter halts until it is reprogrammed when the counter reaches zero. Two Free Running Counters operate in common timer clock (TIMCLK). APB bus clock (PCLK) is used as the timer clock. Also, each Free Running Counter has a pres caler that can divide by 1, 16, or 256. Therefore, the count rate of each Free Running Count er can be controlled by each prescaler. Writing to the Load Register loads the counter with the timer count value. If the timer counter is enabled, the timer decrements at the rate determined in the ti mer clock and in the prescaler setting. When the timer counter has been running, writing to the Load Register restarts the counter immediately with a new value. An alternative way of loading the timer count is to write to Background Load Register. In this way, the current count value is not affected immediately after the writing, and th e counter continues to decrement. Then, in the case where the counter r eaches zero, the timer counter is reloaded with a new load value if it is in Periodic Mode. When the timer count reaches zero, an interrupt is ge nerated. Writing to Interrupt Clear Register clears the interrupt. Also, the interrupt output signal can be masked by Interrupt Mask Register. The current counter value can be read from Value Register at any time. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 346 MB9Axxx/MB9Bxxx Series
2. Architecture 2. Architecture This chapter illustrates the Dual Timer architecture. Figure 2-1 Dual Timer Block Diagram FUJITSU SEMICONDUCTOR LIMITED Prescaler Timer1Load Register Timer1BGLoad Register Timer1Control Register 32/16-bit Down Counter Timer1Value Register Interrupt and Reload Control Interrupt Status Register Masked Interrupt Status Register Interrupt Clear Register Timer1 Free Running Counter APB Interface APB Bus Timer1 Interrupt Request Time r Clock (TIMCLK) Prescaler Timer2Load Register Timer2BGLoad Register Timer2Control Register 32/16-bit Down Counter Timer2Value Register Interrupt and Reload Control Interrupt Status Register Masked Interrupt Status Register Interrupt Clear Register Timer2 Free Running Counter Timer2 Interrupt Request CHAPTER 12: Dual Timer MN706-00002-1v0-E 347 MB9Axxx/MB9Bxxx Series
3. Operation Description 3. Operation Description This chapter describes Dual Timer operations. 3.1 Timer Operating Mode 3.2 Default 3.3 Interrupt Behavior FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 348 MB9Axxx/MB9Bxxx Series
3. Operation Description 3.1. Timer Operating Mode Operating modes are selected from three timer modes based on the settings of the Control Register (TimerXControl)’s mode bit (TimerMode) and one-shot mode bit (OneShot). Table 3-1 Mode Selection Table TimerMode OneShot Selective Mode 0 0 Free-running Mode 1 0 Periodic Mode - 1 One-shot Mode Timer size bit (TimerSize) of the Control Register is us ed to appropriately configure 32-bit or 16-bit counter operation. The ch aracter X in a register name in this chapter indi cates either re gister of Free Running Counter 1 or 2. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 349 MB9Axxx/MB9Bxxx Series
3. Operation Description Free-running Mode When a reset is performed, the timer value is initialized to 0xFFFFFFFF. Then, if the counter is enabled, the count decrements by one at the timer clock (TIMCLK) rising edge. Alternatively, writing to the Load Register (TimerXLoad) loads a new initial counter value. Then, if the counter is enabled, the counter starts to decrement from this loaded value. In 32-bit mode, when the count reaches zero (0x00000000 ), an interrupt is generated. Then, regardless of the Load Register’s value, the counter wraps around to 0xFFFFFFFF. The counter starts to decrement again, and as long as the counter is enable d, this whole cycle is repeated. In 16-bit mode, only the least significant 16 bits of the counter are decremented. When the count reaches 0x0000, an interrupt is generated. Then, regardless of the Load Register’s value, the counter wraps around to 0xFFFF. If the Enable bit (TimerEn) of the Control Register (TimerXControl) is cleared and that the counter is disabled, the counter halts and holds the current value. If the counter is enabled again, the counter continues to decrement from the current value. The counter value can be read from the Va lue Register (TimerXValue) at any time. Figure 3-1 Free-running Mode Operation (32-bit Mode) FUJITSU SEMICONDUCTOR LIMITED Timer Time Counter Value 0x00000000 0xAFFFFFFF 0xFFFFFFFF TimerEn TimerXLoad TimerXRIS Timer Enable Interrupt generated W r ite to Load Register Interrupt generated Reset Release 0x00000000 0xAFFFFFFF Disable Timer Enable Interrupt generated CHAPTER 12: Dual Timer MN706-00002-1v0-E 350 MB9Axxx/MB9Bxxx Series
3. Operation Description Periodic Mode Writing to the Load Register (TimerXLoad) loads an initial counter value. Then, the counter starts to decrement from this value if the counter is enabled. In 32-bit mode, all 32 bits of the counter are decremented. Then, when the count reaches zero (0x00000000), an interrupt is generated. The counter reloads the Lo ad Register value. The counter starts to decrement again. As long as the counter is enabled, this whole cycle is repeated. In 16-bit mode, only the least significant 16 bits of the counter are decremented. When the count reaches 0x0000, an interrupt is generated. Then, the counter reloads the Load Register value. The counter starts to decrement again. As long as the counter is enabled, this whole cycle is repeated. When a new value is written to the Background Load Register (TimerXBGLoad) while the counter is running, the value of the Load Register is also update d to the same value. However, the counter continues to decrement to zero. When the counter reaches zero, it reloads the new value. As long as the Timer is set to Periodic Mode, this new load value is used for each subsequent reload. When a new value is written to the Load Register for loading the value to the counter while the counter is running, the counter value is changed to the new load value at the next timer clock. If the Enable bit (TimerEn) of the Control Register (TimerXControl) is cleared and that the counter is disabled, the counter halts and holds the current value. If the counter is enabled again, the counter continues to decrement from the current value. Figure 3-2 Periodic Mode Operation (32-bit Mode) FUJITSU SEMICONDUCTOR LIMITED Count Value 0x00000000 0xCFFFFFFF 0xFFFFFFFF TimerEn TimerXLoad / TimerXBGLoad TimerXRIS Timer Disable 0x00000000 0xCFFFFFFF Reset Release Write to BG Load Register Interrupt generated Interrupt generated Timer Enable Write to Load Register 0x7FFFFFFF 0x7FFFFFFF Write to Load Register Timer Enable Interrupt generated Time Interrupt generated 0x7FFFFFFF CHAPTER 12: Dual Timer MN706-00002-1v0-E 351 MB9Axxx/MB9Bxxx Series
3. Operation Description One-shot Mode To start the count down sequence in One-shot Mode, a new load value is written to the Load Register (TimerXLoad). If the counter is enabled, it starts to decrement from this value. In 32-bit mode, all 32 bits of the counter are decremented. Then, when the count reaches zero (0x00000000), an interrupt is generated. Then, the counter halts. In 16-bit mode, only the least significant 16 bits of the counter are decremented. When the count reaches 0x0000, an interrupt is generated. Then, the counter halts. In One-shot Mode, writing a new value to the Load Re gister starts the counter again. Then, the counter value is changed to the new load value at the next timer clock. Figure 3-3 One-shot Mode Operation (32-bit Mode) FUJITSU SEMICONDUCTOR LIMITED Count Va lu e Timer Time 0x00000000 0xCFFFFFFF 0xFFFFFFFF TimerEn TimerXLoad Disable TimerX R IS 0x00000000 0xCFFFFFFF Reset Release Write to Load Register Interrupt generated Interrupt generated Interrupt generated Timer Enable 0x7FFFFFFF Write to Load Register 0x7FFFFFFF Timer Enable 0x7FFFFFFF Write to Load Register CHAPTER 12: Dual Timer MN706-00002-1v0-E 352 MB9Axxx/MB9Bxxx Series
3. Operation Description 3.2. Default After the reset, the timer is initialized as shown below: Timer counter disabled Free-running mode selected 16-bit counter mode selected Prescaler in the setting of dividing by 1 Interrupt clear and inte rrupt enable states Load Register set to zero Counter value set to 0xFFFFFFFF FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 353 MB9Axxx/MB9Bxxx Series
3. Operation Description 3.3. Interrupt Behavior This section describes interrupt behaviors. An interrupt is generated when the counter reaches 0x00000000 (in 32-bit mode) or 0xXXXX0000 (in 16-bit mode) in the setting of interrupt enable (IntEnable=1). In 16-bit mode, the most significant 16 bits of the counter are ignored. Writing to Interrupt Clear Register (T imerXIntClr) clears an interrupt. The interrupt signals generated in the Timer module can be masked when Interrupt Enable bit (IntEnable) of the Control Register is set to 0. The raw interrupt state before being masked can be read from Interrupt Status Register (TimerXRIS). Also, the masked interr upt state can be read from Masked Interrupt Status Register (TimerXMIS). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 354 MB9Axxx/MB9Bxxx Series