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2. UART Interrupt 
 
2.4.  Interrupt and flag set timing when transmit FIFO is used 
When the transmit FIFO is used, an interrupt occurs if the FIFO contains no data. 
 Transmit interrupt and flag set ti ming when transmit FIFO is used 
  If the Transmit FIFO contains no data, the FIFO transmit data request bit (FCR1:FDRQ) is set to 1. 
If FIFO transmit interrupts are enabled (FCR 1:FTIE=1), a transmit interrupt occurs. 
   If a transmit interrupt has occurred and you have  written the required data in transmit FIFO, clear the 
interrupt request by setting the FIFO transmit data request bit (FCR1:FDRQ) to 0. 
   The FIFO transmit data request bit (FCR1:FDRQ) is  set to 0 when transmit FIFO becomes full. 
   To check to see if transmit FIFO contains any da ta, read from the FIFO Byte Register (FBYTE). 
If FBYTE=0x00, no data exists in the transmit FIFO. 
 
Figure 2-8 Transmit interrupt timing when transmit FIFO is used 
 
Transmit data
FBYTE
FDRQ 2
A transmit interrupt 
occurred.*1
Data writing in 
transmit FIFO (TDR)
1st byte   2nd byte   3rd byte  ST  SP  ST  SP  ST   SP   ST  4th byte  SP  SP  
01102
 1
Cleared if set to 0.
TDRE
5th byte  
10
The Transmit Data Register is empty.*2
Cleared if 
set to 0.
*1) The FDRQ bit is set to 1 as transmit FIFO is empty.
*2) The TDRE bit is set to “1” as the Transmit Shift Register and the Transmit Buffer Register  contain no data.  A transmit interrupt 
occurred.*1
  
   
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3. UART Operation 
 
3. UART Operation 
UART operates in bi-directional serial asynchronous communications in mode 0 and 
master/slave multiprocessor communications in mode 1. 
 UART operation 
  Transmit/receive data format 
  Transmit/receive data always starts w ith a start bit, followed by transmission/reception of data with the 
specified data bit length, and ends wi th at least one-bit long stop bit. 
   The BDS bit of the Serial Mode Re gister (SMR) determines the data transmit direction (LSB first or 
MSB first). If parity is used, the parity bit is always  placed between the last data bit and the first stop bit. 
   In operation mode 0 (normal mode), selection is possible to use or not to use parity. 
   In operation mode 1 (multiprocessor mode), no parity  is added, and instead, the AD bit is added.   
Figure 3-1  shows the transmit/receive data fo rmats for operation mode 0 and 1. 
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3. UART Operation 
 
Figure 3-1 Example transmit/receive data format (operation mode 0/1) 
 
[Operation mode 0]
[Operation mode 1]
ST : Start bit
SP : Stop bit
P : Parity bit
AD : Address bit
D : Data bit
Without P
With PData: 8 bits
ST D0 D1 D2 D3 D4 D5 D6 D7 SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 D7 SP1
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP1
ST D0 D1 D2 D3 D4 D5 D6 SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 SP1
ST D0 D1 D2 D3 D4 D5 D6 P SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 P SP1 Without P
With P
Data: 7 bits
ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP1
ST D0 D1 D2 D3 D4 D5 D6 AD SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 AD SP1 Data: 8 bits
Data: 7 bits
  
 
 
  The above  fi

gure shows formats when the data length is set to 7 or 8 bits. (In operation mode 0, the data 
length can  b

e set between 5 and 9 bits.) 
   If the BDS bit of the Serial Mode Register (SMR) is  set to 1 (MSB first), the bits are processed from 
D7, and then D6, D5, ... D1, and D0 (P), in that order. 
   If the data length is set to X bits, the lower X bit  of the Transmit/Receive Data Register (TDR/RDR) is 
enabled. 
 
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3. UART Operation 
 
 Data transmission 
  If the transmit data empty flag bit (TDRE) of the Serial Status Register (SSR) is 1, the transmit data 
can be written in the Transmit Data Register (TDR).  (When transmit FIFO is enabled, transmit data can 
be written even if TDRE=0.) 
   If transmit data is written in the Transmit Data Register (TDR), the transmit data empty flag bit 
(SSR:TDRE) is set to 0. 
   Setting the transmission enable bit of the serial contro l register (SCR:TXE) to 1 causes transmit data to 
be loaded to the transmit shift register, followed by  sequential transmission starting with the start bit. 
   When transmission starts, the transmit data empty flag bit (SSR:TDRE) is set to 1 again. If transmit 
interrupts are then enabled (SCR:TIE=1), a transmit interrupt is generated. In the interrupt processing, 
the next transmit data set can be written in the Transmit Data Register, 
 
 
  As the transmit  d

ata empt
 y flag bit (SSR:TDRE) is initially set to 1, a transmit interrupt occurs as soon 
as transmit interrupts are enabled (SCR:TIE). 
   As the FIFO transmit data request bit (FCR1:FDRQ) is  initially set to 1, a transmit interrupt occurs as 
soon as FIFO transmit interrupts are enabled (FCR1:FTIE=1). 
 
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3. UART Operation 
 
 Data reception 
  When reception is enabled (SCR:RXE=1) , the interface performs reception. 
   Upon detection of the star t bit, one-frame reception takes place acco rding to the data format set in the 
extended communications control register (ESCR:PE N, P, L2, L1, L0) and serial mode register 
(SMR:BDS). A start bit is detected when falling (E SCR:INV=0) is detected after passing the noise 
filter (with the majority value applied after sampling seri al data input three times with the bus clock) or if 
rising (ESCR:INV=1) is detected and LOW is detected for the data passing the sampling point.   
   When one-frame reception is completed, the receive da ta full flag bit (SSR:RDRF) is set to 1. If 
receive interrupts are then enabled (SCR:RI E=1), a receive interrupt is generated. 
   To read received data, perform reading of the received data after one- frame data reception is completed 
and check the state of the error flag of the Serial St atus Register (SSR). Handle the receive error if it is 
occurring. 
   Reading of the received data causes the receive data  full flag bit (SSR:RDRF) to be cleared to 0. 
   If receive FIFO is enabled, the receive data full flag  bit (SSR:RDRF) is set to 1 when the number of 
received frames has reached the value set for receive FBYTE. 
   If all of the following conditions are satisfied and if th e receive idle state continues for more than 8 baud 
rate clocks, the interrupt flag (RDRF) is set to 1. 
  The receive FIFO idle detection enable bit (FRIIE) is 1. 
   The number of data sets stored in the recei ve FIFO does not reach the transfer count. 
If the RDR data is read during counting of 8 clocks, this counter is reset to 0, and counting for 8 
clocks is restarted. If receive FIFO is disabled, this counter is reset to zero (0).  If data remains in the 
receive FIFO and if receive FIFO is en abled, the data counting is restarted. 
   If receive FIFO is enabled, receive FIFO does not  store data in which an error has occurred when the 
error flag of the Serial Status Register (SSR) is set  to 1. Also note that the receive data full flag bit 
(SSR:RDRF) is not set to 1. (However, the RDRF fl ag is set to 1 in an overrun error.) What the 
receive FBYTE indicates is the number of data sets  received normally before the error occurred. Unless 
the error flag of the Serial Status  Register (SSR) is cleared to 0, receive FIFO is not enabled. 
   If receive FIFO in enabled, the receive data full flag  bit (SSR:RDRF) is cleared to 0 when all data in 
receive FIFO is out. 
 
 
  Data in the Re ceive Data

 Register (RDR) becomes va lid when the receive data register full flag bit 
(SSR:RDRF) is  set to 

1 and no receive error occurs (SSR:PE, ORE, FRE=0). 
   Although a noise filter is built in (with the majority  value applied after sampling serial data input three 
times with the bus clock) , wrong data may be received is any  noise passes through the filter. As a 
countermeasures, you can design the board so as not to allow noise to pass through this filter or perform 
communications so that noise that has passed may not cause any problem (by adding check sum of data 
at the end and resending the data  if any error occurs, for example). 
   During reception, if the following is  detected at the same time as the stop bit sampling point or before the 
1-2 bus clock, the relevant edge becomes invalid, which may disable normal reception of the next data. 
To output frames continuously, adequate intervals are required between frames. 
  The falling edge of serial data (When ESCR:INV=0) 
   The rising edge of serial data (When ESCR:INV=1) 
 
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3. UART Operation 
 
 Clock selection 
  You can use either an internal or external clock. 
   To use the external clock, set SMR:EXT to 1. IN th is case, the external clock is subject to frequency 
division by the baud rate generator. 
  Start bit detection 
  In asynchronous mode, the start bit is recognized based on detection of the falling edge of the SIN signal. 
For that reason, reception is  not started unless the falling edge of the SIN signal is input even if reception 
is enabled (SCR:RXE=1). 
   Upon detection of the  start bits falling edge, the receive reload counter of the baud rate generator is reset 
and reloaded to start countdown. Thus, sampling always takes place in the middle of data. 
 
 
Start bit
Receive 
sampling clock SIN
SIN
(Over-Sampled)
Data bit
SEDGE 
(Internal signal)Reload 
counter resetData sampling
A bit time   
 
  Stop bit 
  You can select the bit length to be between one and four.   
   The receive data full flag bit (SSR:RDRF) is set  to 1 upon detection of the first stop bit. 
 Error detection 
  In operation mode 0, parity, overrun and framing errors can be detected. 
   In operation mode 1, overrun and framing errors can  be detected but parity errors cannot be detected. 
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3. UART Operation 
 
 Parity bit 
  The parity bit can only be added in operation mode 0. The parity enable bit (ESCR:PEN) can be used to 
specify use or non-use of parity and the parity selection bit (ESCR:P) to set even-number parity or 
odd-number parity. 
   Parity cannot be used in operation mode 1. 
Figure 3-2  shows transmit/receive data when parity is enabled. 
Figure 3-2 Operation when parity is enabled 
 
Receive data 
(Mode 0)
Transmit data  (Mode 0)
Transmit data  (Mode 0) ST D0 D1 D2 D4 D5 D6 D7 SP
SMR : PE
During reception , a parity error occurs 
through even-number parity check.
(ESCR:P=0)
D3  P
Transmit of even-number parity bits
(ESCR:P=0)
Transmit of odd-number parity bits
(ESCR:P=1)
Note : Parity cannot be used in operation mode 1.
ST : Start bit SP : Stop bit
With parity (ESCR:PEN = 1), 8-bit long
  
 
 Data signaling system 
  By setting up the INV bit of the extended communications control register, you can select either the NRZ 
(Non Return to Zero) signaling system (ESCR:INV=0) or inverted NRZ signaling system 
(ESCR:INV=1). 
Figure 3-3  shows the NRZ and inverted NRZ signaling systems. 
Figure 3-3 NRZ (Non Return to Zero) signaling system and inverted NRZ signaling system   
 
SIN (NRZ)
INV = 0
SIN (Inverted NRZ) INV = 1
SIN (Inverted NRZ) INV = 1
SOT (NRZ)
INV = 0
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
  
 
  Data transfer system 
  For the data bit transfer method, either LSB first or MSB first can be selected. 
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3. UART Operation 
 
 Hardware flow control 
When flow control is enabled (ESCR:FLWEN=1 ), UART performs hardware flow control. 
   During data transmission 
If 
CTS  is HIGH after data is transmitted, the next  data is not transmitted even if the transmit buffer 
contains data (TDRE=0) and the process waits until 
CTS  is set to LOW. To have transmission 
wait, input HIGH in 
CTS  before the stop bit transmission is completed. Transmission continues up 
to the stop bit even if HIGH is input in 
CTS during transmission. 
Figure 3-4 Hardware flow control during data transmission  (SMR:SBL=0, ESCR:ESBL=INV=PEN=L2=L1=L0=0) 
ST SPST SPTransmit data
TDRE
Data writing in TDR
Transmission in wait state
CTS
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
 
 
  During data reception 
   If FIFO is not used 
Upon reception of data one bit before  the stop bit, HIGH is output to 
RTS. After received data is 
read, LOW is output to 
RTS. 
Figure 3-5 Hardware flow control during data reception (with FIFO unused)  (SMR:SBL=0, ESCR:ESBL=INV=PEN=L2=L1=L0=0) 
ST SPST SPReceive data
RDRF
Reading from RDR
RTS
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
 
 
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3. UART Operation 
 
  If FIFO is used 
If SSR:RDRF is not set (the specified number of  data sets are not received in receive FIFO), 
RTS 
outputs HIGH upon reception of data one bit before the stop bit, but 
RTS outputs LOW upon 
detection of the stop bit. (For period 1) 
If SSR:RDRF is set (the specified number of  data sets are received in receive FIFO), 
RTS outputs 
HIGH upon reception of data one  bit before the stop bit. 
RTS  outputs LOW after all data is 
read from receive FIFO. (For period 2) 
Figure 3-6 Hardware flow control during data reception (with FIFO used)  (SMR:SBL=0, ESCR:ESBL=INV=PEN=L2=L1=L0=0) 
ST D0Receive data
RDRF
The entire data is 
read from receive 
FIFO buffer.STSP SPST
Period 
1Period 2
RTS
D0
D6 D7 D6 D7 D0
 
 
 
  Whe
n receive ope ration 

is disabled (RXE=0), the 
RTS  signal is fixed to LOW. 
   If both conditions below are satisfied  when receive FIFO is used and if the receive idle state continues 
for more than 8 baud rate clocks, RDRF is set to 1 but LOW is maintained for the 
RTS signal. 
   The receive FIFO idle detection  enable bit (FCR1:FRIIE) is 1. 
   The preset data amount is not received an d some data remains in receive FIFO. 
   Performing programmable resetting (SCR:UPCL=1) clears the 
RTS  signal to LOW. 
 
 
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4. Dedicated Baud Rate Generator 
 
4.  Dedicated Baud Rate Generator 
For the UART transmit/receive clock source, either of the following can be selected. 
- Dedicated baud rate generator (reload counter) 
- An external clock input to the baud rate generator (reload counter) 
 Selecting the UART baud rate 
Select one of the following two baud rates. 
  Baud rate obtained by dividing an internal clock using the dedicated baud 
rate generator (reload counter) 
This generator provides two internal reload counters, which support transmitting and receiving serial clocks 
respectively. To select the baud rate, specify the 15-bit reload value using Baud Rate Generator Registers 1 
and 0 (BGR1 and BGR0). 
Each reload counter divides an internal clock by the set value. 
To set the clock source, select  an internal clock (BGR1:EXT=0). 
 Baud rate obtained by dividing an ext ernal clock using the dedicated baud 
rate generator (reload counter) 
Use an external clock for the clock source of the reload counter. 
To select the baud rate, specify the 15-bit reload value using Baud Rate Generator Registers 1 and 0 (BGR1 
and BGR0). 
Each reload counter divides an external clock by the set value. 
To set the clock source, select use of an external clock and the baud rate generator clock (BGR1:EXT=1). 
This mode is designed for cases where an oscillato r with a divided non-standard frequency is used. 
 
    Set th e e

xternal clock (BGR1:EXT=1) while the reload counter is suspended (BGR1/0=15 h00). 
   If an ext e

rnal clock is selected (BGR1:EXT=1), its HIGH and LOW signals must have a width at least of 
two bus clocks. 
 
 
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CHAPTER  19-2: UART  \050Async  Serial Interface\051 
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