Fujitsu Series 3 Manual

							 
2. Configuration 
 
2. Configuration 
Figure 2-1 shows the block diagram of the CAN controller. 
Figure 2-1 CAN controller block diagram 
CAN_TX
CAN control unitCAN_RX
Message RAM
CAN Control Register
CPU interface
Message handler
ClockResetControlDataOUTDataIN
Address[7:0]
CAN controller
Interrupt
 
   CAN control unit 
Controls the CAN protocol and the serial registers fo r serial/parallel conversion to transfer send/received 
messages. 
   Message RAM 
Stores message objects 
   Registers 
All registers used by CAN. 
   Message handler 
Controls the message RAM and CAN control unit. 
   CPU interface 
Controls the internal bus interface. 
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3. CAN Controller Operations 
 
3. CAN Controller Operations 
This section explains the operations and functions of the CAN controller. 
Following functions are included: 
  Message objects 
   Message transmission 
   Message reception 
   FIFO buffer function 
   Interrupt function 
   Bit timing 
   Test mode 
   Software initialization 
 
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3.1. Message objects 
The following explains message objects and the interface of the message RAM. 
 Message objects 
The configuration of message objects in the message RAM (excluding the MsgVal, NewDat, IntPnd, and 
TxRqst bits) is not initialized by a hardware reset. Initialize the message objects by the CPU, or set the 
MsgVal bit to disable (MsgVal = 0). Configure the CAN Bit Timing Register while the Init bit in the CAN 
Control Register is 1. 
A message object must be configured by programming message interface registers (the IFx Mask Register, 
IFx Arbitration Register, IFx Message Control Register , and IFx Data Register), and then writing a message 
number to the corresponding IFx Command Request Re gister. By writing the message number, the interface 
register data will be transferred  to the addressed message object. 
When the Init bit in the CAN Control Register is cleared to 0, the CAN controller starts operation. The 
received data that have passed acceptance filtering  are stored into the message RAM. Messages with 
pending transmission requests are transferred from  the message RAM to the shift register in the CAN 
controller, and then sent to the CAN bus. 
The CPU reads the received messages and updates outgoi ng messages via message interface registers. The 
CPU is interrupted according to the configuration of the CAN Control Register and IFx Message Control 
Register (message object). 
  Data transfer from/to message RAM 
When data transfer starts between the message interface registers and message RAM, the Busy bit in the 
IFx Command Request Register is set to 1. After the tr ansfer has finished, the Busy bit is cleared to 0. 
(See  Figure 3-1 ) 
The  IFx Com
m

and Register selects whether to transfer complete data or only partial data of one message 
object. The structure of the message RAM does not allow the writing of single bits/bytes of one message 
object. The complete data of one message object is al ways written to the message RAM. Therefore, the data 
from the message interface registers to the message  RAM is transferred in a read-modify-write cycle. 
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Figure 3-1 Data transfer between the message interface registers and message RAM 
Start
Write to IFx Command Request Register
Busy = 1
WR/RD = 1
Read from message RAM to message interface registers
Write from message interface registers to  message RAM
Read from message RAM to message interface registers
Busy = 0
No Yes
Yes
No
 
 
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3.2. Message transmission 
The following explains how to configure the send message objects, and about the transmission. 
 Sending messages 
If there is no data transfer between the message interf ace registers and message RAM, the MsgVal bit in the 
CAN Message Valid Register and the TxRqst bit in  the CAN Transmit Request Register are evaluated. A 
valid message object with the highest priority of pend ing transmission requests is transferred to the shift 
register for transmission. Then the NewDat bit of the message object is reset to 0. 
When the transmission has finished successfully, and if  there is no new data in the message object (NewDat 
= 0), the TxRqst bit is reset to 0. If TxIE is set to 1, then the IntPnd bit is  set to 1 after a successful 
transmission. If the CAN controller lost the arbitratio n on the CAN bus, or if an error occurred during 
transmission, the message is resent imme diately when the CAN bus becomes idle. 
 Transmission priority 
The transmission priority of the message objects is  determined by the message number. Message object 1 
has the highest priority, while message object 32 (the largest number of the installed message objects) has 
the lowest priority. If two or more transmission requests are pending, they are tran sferred in the order of 
corresponding message number from smallest to largest. 
 
 
  In one  o

f the following conditions, the messages may not be sent until any of the events described below 
occurs.  Condition s

 :  (1) A message buffer with the lowest priority is used for transmission. 
  (2) The TxRqst bit was previously set to 1, but is set to 0 to abort transmission. 
  (3) The TxRqst bit is set to 1 again at the timing of (2). 
Events :  - A valid message flows on the CAN bus. 
  - A transmission request is issued to another message buffer. 
  - CAN is initialized by the Init bit. 
If canceling the transmission is required to suit  system operations, execute the following steps. 
1.  Execute one of the  following steps. 
   Do not use a message buffer with the lowest priority as a send message buffer. 
   After aborting the transmission, generate any of the above events. 
 
2.  Set the TxRqst bit to 1 again. 
 
   If the message objects of ID28-0, DLC3-0, Xtd, and Data7-0 are changed while the TxRqst bit is 1, 
message objects before and after the change are mixed  for transmission, or the message objects after the 
change may not be transmitted. Therefore, be sure to change them while the TxRqst bit is 0. 
 
 
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 Configuring a send message object 
Ta b l e  3 - 1  shows how a send object should be initialized. 
Table 3-1 Initialization of a send message object 
MsgVal Arb Data Mask EoB Dir NewDatMsgLstRxIETxIEIntPnd RmtEn TxRqst 
1 0 1 1 0 0 0 0 appl. appl. appl. appl.appl. 
 
The IFx Arbitration Register (ID28-0 and Xtd bit), given by the application, defines the ID and the type of 
the outgoing message. 
If the standard frame (11-bit ID) is set, then ID28 to  ID18 are used, and ID17 to ID0 are ignored. If the 
extended frame (29-bit ID) is set, then ID28 to ID0 are used. 
If TxIE bit is set to 1, then the IntPnd bit is set to 1 after a successful transmission of the message 
object. 
If the RmtEn bit is set to 1, the TxRqst bit is set  to 1 after receiving the corresponding remote frame, 
and a data frame is sent automatically. 
The data register (DLC3-0, Data0-7) settings are given by the application. 
When Umask is set to 1, the IFx Mask Register  (Msk28-0, UMask, MXtd, and MDir bits) is used to 
receive remote frames with the IDs grouped by the  mask setting, and then enable the transmission (by 
setting the TxRqst bit to 1). For details, see Remote Frame in  3.3 Message reception. 
 
  The Di r 

bit in the IFx Mask Register must not be mask-enabled. 
   
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 Updating a send message object   
The CPU can update the data of a send message object via the message interface registers. 
The send message object data is written by four bytes  of the corresponding IFx data register (in the unit of 
IFx data register A or IFx data register B). Therefore, the send message object cannot be changed by a 
single byte. 
To update 8-byte data, write 0x0087 to the IFx Command Mask Register, and the message number to the 
IFx Command Request Register. This concurrently updates the send message object data (of 8-byte) and 
write 1 to the TxRqst bit. 
If both the NewDat and TxRqst bits are set to 1, the NewDat bit is reset to 0 once the transmission is 
started. 
 
 
  To  

update data, update it by four bytes of the IFx Data Register A or IFx Data Register B. 
   If the me ssage 

objects of ID28-0, DLC3-0, Xtd, and Data7-0 are changed while the TxRqst bit is 1, 
message objects before and after the change are mixe d for transmission, or the message objects after 
the change may not be transmitted. Therefore, be sure to change them while the TxRqst bit is 0. 
 
 
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3.3. Message reception 
The following explains how to configure the receive message object and about the reception. 
 Acceptance filtering  for received messages 
When the arbitration and control field (ID + IDE + RTR + DLC) of a message is completely shifted into the 
shift register of the CAN controller, scanning of th e message RAM is started to compare matching with a 
valid message object. 
Then the arbitration field and mask data (including MsgVal, UMask, NewDat, and EoB) are loaded from a 
message object in the message RAM, and the message obje ct is compared with the arbitration field of the 
shift register including mask data. 
This operation is repeated until a matching is detected  between a message object and the arbitration field of 
the shift register, or until the last word of the message RAM is reached.When a matching is detected, 
scanning of the message RAM is stopped, and the CAN controller processes data depending of the type of 
the received frame (data frame or remote frame). 
  Reception priority 
The reception priority of the messa ge objects is determined by the message number. Message object 1 has 
the highest priority, while message object 32 (the largest number of the installed message objects) has the 
lowest priority. If two or more objects are matched in  the acceptance filtering, therefore, the object with the 
smallest message number becomes the receive message object. 
  Data frame reception 
The CAN controller transfers the received message from the shift register into  the message RAM of the 
message object matched in the acceptance filtering. The stored data includes all arbitration fields and the 
data length code as well as data bytes. This is implem ented (to keep the ID and the data bytes) even if the 
IFx Mask Register is used for masking. 
The NewDat bit is set to 1 upon the reception of new data. When the CPU reads the message object, reset 
the NewDat bit to 0. If the NewD at bit has already been set to 1 upon the reception of a message, the 
MsgLst is set to 1 indicating that the previous data was lost. 
If the RxIE bit has been set to 1, reception of a me ssage buffer causes the IntPnd bit in the CAN Interrupt 
Pending Register to be set to 1. Then the TxRqst bit of the message object is reset to 0. This is 
implemented to prevent transmission of a remote frame  when the requested data frame is received during 
the transmission. 
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 Remote frame 
One of the following three operations  is selected when a remote frame is received. The selection depends on 
how the matching message object is configured. 
1.  Dir = 1 (Direction = Send), RmtEn = 1, UMask = 1 or 0 
Receives the matched remote frame, sets only the  TxRqst of this message object to 1, and 
automatically replies (sends) data frame to the remote frame. (Other than the TxRqst bit, the message 
object remains unchanged.)   
2.  Dir = 1 (Direction = Send), RmtEn = 0, UMask = 0 
Does not receive an incoming remote frame, even if  it matches the message object, and disables the 
remote frame. (The TxRqst bit of the message object remains unchanged.) 
3.  Dir = 1 (Direction = Send), RmtEn = 0, UMask = 1 
If an incoming remote frame matches the message object, the TxRqst bit of the message object is set to 
0, and the remote frame is handled as if it were  a received data frame. The received arbitration field 
and control field (ID + IDE + RTR + DLC) are stored  into the message object in the message RAM, and 
the NewDat bit of this message object is set to  1, The data field of the message object remains 
unchanged. 
  Configuring a receive message object 
Ta b l e  3 - 2  shows how a receive message object should be initialized. 
Table 3-2 Initialization of a receive message object 
MsgVal Arb Data Mask EoB Dir NewDatMsgLstRxIETxIEIntPnd RmtEn TxRqst 
1 0 0 1 0 appl.0 0 appl. appl. appl. 0 0 
 
The IFx Arbitration Register (ID28-0 and Xtd bit) is given by the application. The register defines the ID 
and the type of a received message,  used for the acceptance filtering. 
If the standard frame (11-bit ID) is set, then ID28 to ID18 are used, and ID17 to ID0 are ignored. When a 
standard frame is received, ID17 to ID0 are reset to 0.  If the extended frame (29-bit ID) is set, then ID28 
to ID0 are used. 
When the RxIE has been set to 1, and when a receive d data frame is stored into the message object, then 
the IntPnd bit is set to 1. 
The data length code (DLC3-0) is given by the application. When the CAN controller stores the received 
data frame into the message object,  it stores the received data length code and eight bytes data. If the data 
length code is less than eight, unspecified data is written to the remaining bytes of the message object. 
When Umask is set to 1, the IFx Mask Register (Msk 28-0, UMask, MXtd, and MDir bits) is used to allow 
the reception of data frames with  the IDs grouped by the mask setting. For details, see Data Frame 
Reception in  3.3 Message reception . 
 
  The Di r 

bit in the IFx Mask Register must not be mask-enabled. 
   
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 Handling a received message 
The CPU can read a received message any ti me via the message interface registers. 
The following shows an example of handling a received message. Write 0x007F to the IFx Command 
Register, and a message number of the message object to the IFx Command Request Register. This 
procedure transfers a received message of the specifi ed message number from the message RAM to the 
message interface registers. Then the  NewDat bit and IntPnd bit of the message object can be cleared to 0 
according to the configuration of  the IFx Command Mask Register. 
An incoming message is received if it is matched in  the acceptance filtering. If the message object uses a 
mask for acceptance filtering , the masked data is excluded from  the acceptance filtering to determine 
whether or not the message should be received. 
The NewDat bit indicates whether a ne w message has been received since the last time the message object 
was read. 
The MsgLst bit indicates that the previous received data  was lost because the next data is received before 
the previous data is read from the message object. The MsgLst bit is not automatically reset. 
During transmission of a remote frame, if a data fra me matched in the acceptance filtering is received, the 
TxRqst bit is automatically reset to 0. 
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