Fujitsu Series 3 Manual

							 
3. Explanation of Operations 
 
3.3. Reset Sequence 
This model initiates the hardware the program and hardware operations starting with the initial 
state when a reset cause is cleared.   
A series of operations starting with the reset and ending with the initiation of the operations is 
called a reset sequence.   
The following explains a reset sequence. 
 State Transition Diagram for Resets 
The following diagram shows a transition of reset states. The detailed operations are given in the 
following sections. 
Power up
Generate reset 
cause
PONR
Issue device reset
Clear reset cause PONR
Run mode
Generate reset cause
INITX, LVDH
Clear reset cause INITX, LVDH
Generate reset causeSWDGR, HWDGR,  CSVR, FCSR
Clear reset cause
SWDGR, HWDGR,  CSVR, FCSR
Determine operation mode
Reset vector fetch
Start program
Generate reset  cause
SRST
Wait time required until oscillation of  high-speed CR has become stable, etc.
Initialize all circuitsInitialize the range of 
reset for each reset  causeInitialize the range of 
reset for each reset  causeInitialize the range of 
reset for each reset  cause
Clear reset cause
SRST
Clear device reset
 
 
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3. Explanation of Operations 
 
1. Capturing reset causes 
Reset causes are captured and retained until a reset is issued to the device. 
2.  Issuing resets 
When a reset is ready to be issued, a device internal reset is issued. 
3.  Clearing resets 
When a reset cause is cleared, a device internal reset is extended for the amount of time required to clear 
the reset (for example, a wait required until oscilla tion of a high-speed CR has become stable). When 
the extended period of time has expired, the reset is cleared. 
4.  Determining operation mode 
The operation mode is determined  as PONR, LVDH or INITX is cleared and notified to each piece of 
the hardware. Any other reset causes do not  cause the operation mode to change. 
5.  Reset vector fetch 
After a device internal reset is cleared, the CPU  starts fetching a reset vector. The CPU fetches the 
obtained reset vector into the program counter and starts programmed operations. 
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3. Explanation of Operations 
 
3.4.  Operations After Resets are Cleared 
 PONR, LVDH, INITX, HWDG R, SWDGR, CSVR, FCSR 
Figure 3-1 provides an example of the operation waveform  after a cause of INITX pin input reset ha s been 
cleared. 
Figure 3-1 Operation Waveform After INITX Pin Input Reset has been Cleared 
INITX
Internal reset
Oscillation of 
low-speed CR
Wait time required until oscillation of high- speed CR has become stable
Oscillation of 
high-speed CR
Dozens cycle
Start operation
Clear cause 

 SRST 
Figure 3-2  shows an operation waveform after a software reset has been cleared. 
Figure 3-2 Operation Waveform After a Software Reset has been Cleared 
SRST
Internal reset
HCLK
Dozens cycle
Start operation
Clear 
cause
 
 
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4. Registers 
 
4. Registers 
This section explains the configuration and functions of the registers. 
 Register list 
 
Abbreviation Register  name See 
RST_STR Reset cause register  4.1 
 
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4. Registers 
 
4.1.  Reset Cause Register (RST_STR: ReSeT STatus Register) 
The reset cause register shows causes of resets that have just occurred and initializes values 
upon power up. 
Reading the register clears all bits.   
It stores all reset causes that have been generated until after it has been read upon power up. 
 
bit 15 14 13 12 11 10 9 8 
Field Reserved SRST 
Attribute  - - -  - - - - R 
Initial value  - - -  - - - - 1b0 
           
Bit  7 6 5  4 3 2 1 0 
Field FCSR  CSVR HWDT SWDT Reserved Reserved INITX  PONR 
Attribute R R R  R - - R R 
Initial value  1b0 1b0 1b0  1b0 - - 1b0 1b1 
  Note:  Is the value of the initial value after power-up. 
[bits 15:9] Reserved:  These are reserved bits and read value has no meaning. 
[bit8] SRST: Software reset flag  Indicates a reset that is generated by one writing to the reset control register (SYSRESETREQ). 
When a software reset is generated, SRST is enabled (SRST = 1). 
bit Description 
0  A software reset has not been issued. 
1 A software reset has been issued. 
 
[bit 7] FCSR: Flag for anomalous frequency detection reset (FCSR)  Indicates a reset when an anomalous frequency is detected in the main crystal oscillator. 
When the frequency of the main crystal oscillator is outs ide of a given setting, a reset is issued and FCSR is 
enabled (FCSR = 1). 
bit Description 
0  An anomalous frequency detection reset has not been issued. 
1 An anomalous frequency detection reset has been issued. 
 
[bit 6] CSVR: Clock failure detection reset flag  Indicates a reset when a failure is detected in the main or sub crystal oscillator. 
If a stop is detected, a reset is issued and CSVR is enabled (CSVR = 1). 
bit Description 
0  A clock failure detection reset has not been issued. 
1 A clock failure detection reset has been issued. 
Note:  Please refer to another chapter  Clock superv isor  for the method of judging whether the main 
oscillation or the suboscillation broke down.   
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4. Registers 
 
[bit 5] HWDG: Hardware watchdog reset flag Indicates a reset from the hardware watchdog timer. 
If the timer underflows, a reset is issu ed and HWDT is enabled (HWDT = 1). 
bit Description 
0 A hardware watchdog reset has not been issued. 
1 A hardware watchdog reset has been issued. 
 
[bit 4] SWDG: Software watchdog reset flag  Indicates a reset from the software watchdog timer. 
If the timer overflows, a reset is issu ed and SWDT is enabled (SWDT = 1). 
bit Description 
0 A software watchdog reset has not been issued. 
1  A software watchdog reset has been issued. 
 
[bit 3:2] Reserved:  It is a reserved bit and read value has no meaning. 
[bit 1] INITX: INITX pin input reset flag  Indicates a reset that is externally input. 
If a reset is externally input, INITX is enabled (INITX = 1). 
bit Description 
0  An INITX pin input reset has not been issued. 
1 An INITX pin input reset has been issued. 
 
[bit 0] PONR: Power-on reset/low-voltage detection reset flag  Indicates a reset at power up and when a low-voltage is detected. 
If a rising edge of power supply or a low-voltage is detected, a reset is issued and PONR is enabled (PONR 
= 1). 
bit Description 
0  A power-on reset or low-voltage detection reset has not been issued. 
1 A power-on reset or low-voltage detection reset has been issued. 
 
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4. Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Resets 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  18 
 
This register is initialized by a power-on reset or low- voltage detection reset. It is not initialized by any 
other reset causes. Reading th e register clears all bits. 
 
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1. Overview 
 
Chapter: Low-voltage Detection 
This chapter explains the functions and operations of the Low-voltage Detection Circuit. 
 
1.
 Overview 
2. Configuration 
3. Explanation of Operations 
4. Setup Procedure Examples 
5. Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFLVD-E01.2 
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CHAPTER  4: Low-voltage  Detection 
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1. Overview 
 
1. Overview 
The Low-voltage Detection Circuit monitors the power supply voltage, and generates reset 
and interrupt signals when the power supply voltage falls below the detection voltage. 
 Overview of Low-volt age Detection Circuit 
  Operations of Low-voltage Reset Circuit 
  This circuit monitors the power supply voltage (VCC) and generates a reset signal when the power 
supply voltage falls below the specified value. 
   This circuit always monitors the power supply voltage. 
   This circuit monitors the power supply voltage even in standby modes. 
   This circuit generates a reset signal when the reduction of the power supply voltage is detected in 
standby modes. 
 
  Operations of Low-voltage Interrupt Circuit 
  This circuit monitors the power supply voltage (VCC)  and generates an interrupt signal when the power 
supply voltage falls below the specified value. 
   This circuit allows selection of whether to enable or  stop operations. The initial value is set to disable. 
   This circuit allows specification of the detection voltage. 
   This circuit can monitor the power supply voltage even in standby modes. 
   This circuit returns from standby mode when the reduction of the power supply voltage is detected in the 
standby mode. 
 
 
  If a low-voltage d e

tection interru
 pt is enabled or the detection voltage is specified for a low-voltage 
detection interrupt, this circuit starts VCC voltage  monitoring after the stabilization wait time of the 
Low-voltage Detection Circuit has lapsed. 
For the stabilization wait time of the Low-voltage  Detection Circuit, refer to Data Sheet. 
   This circuit does not conduct monitoring the power supply voltage if PCLK2 is gated by TIMER mode, 
STOP mode, or PBC2_PSR Register while waiting for the stabilization of the Low-voltage Detection 
Circuit. After the status flag is read and the stabilization wait time has lapsed, change to the desired 
mode. 
   The Low-voltage Detection Voltage Control Register (LVD_CTL) is write-protected to prevent a writing 
error. To release write protection mode, write  0x1ACCE553 to the Low-voltage Detection Voltage 
Protection Register (LVD_RLR). 
 
 
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