Fujitsu Series 3 Manual

							 
4. Registers of Multifunction Timer 
 
4.1.  Individual Notation and Common Notation of Channel Numbers in Descriptions of Functions 
This section explains the individual notation and common notation of channel numbers in 
descriptions of the functions in this chapter. 
As the multifunction timer unit contains multiple blocks  of the same function and consists of multiple 
channel circuits, there are some common matters across the channels.   
Where there is no need to distinguish among the  channels, and functions that are common to all the 
channels are to be explained, a notation without channel numbers and a notation with parentheses (common 
notation) are used to avoid repeated explanations and simplify their explanation. 
Where there is a need to make distinctions in explaining operation among channels, I/O signals or control 
registers, a notation clearly stating channel numbers (individual notation) is used in such explanation. 
The notation rules and examples are provided below. 
   Where channel numbers are notated directly , that indicates individual notation. 
This notation indicates that the oper ation, I/O signal or control register of the corresponding channel is 
explained. 
   Some control registers control 2 channels at the same time. In such cases, the two corresponding channel 
numbers are stated in individual notation to distinguish between them. 
   Where channel numbers are omitted from a not ation, that indicates the common notation. 
This notation indicates that the operation, I/O signal or control register which is common to all the 
channels is explained to omit the repetition of such explanation. 
   Where channel numbers are stated w ith a figure in parentheses, that indicates the common notation for 
some channels. 
Where there is a need for distinguishing between even-numbered channels and odd-numbered channels 
among the channels mounted, (0) and (1) are stated respectively. 
In this case, (0) indicates that a  function that is common to the even-numbered channels is explained, 
while (1) indicates that a function that is comm on to the odd-numbered channels is explained. 
  Example 1:  ICU-ch.3 of MFT unit 0 can select the calibration input of the internal CR oscillator. 
Example 1 is an example of the individual notation, which indicates that the calibration input of the internal 
CR oscillator can be selected by only ICU-ch.3 of MFT unit 0. This notation indicates that the calibration 
input of the internal CR oscillator cannot be selected by ICU-ch.0 to ch.2 of MFT unit 0 or ICU ch.0 to ch.3 
of other MFT units.  Example 2:  The ICFS10 register is a register that selects  FRT to be connected to ICU-ch.1 and ICU-ch.0. 
Example 3:  The ICFS32 register is a register that selects  FRT to be connected to ICU-ch.3 and ICU-ch.2. 
Examples 2 and 3 are examples of the individual notatio n that states a control register (ICFS) with two 
channel numbers (10 and 32). 
Example 4:  The ICFS register is a re gister that selects FRT to be connected to ICU. 
Example 4 is an example of the common notation that omits the channel numbers of the control register 
(ICFS). What the description explains  means that similar to Examples 2 and 3, repeated explanations are 
omitted by the common notation. 
Example 5:  ICFS10.FSI0[3:0] is a register that selects FRT to be connected to ICU-ch.0. 
Example 6:  ICFS10.FSI1[3:0] is a register that selects FRT to be connected to ICU-ch.1. 
Example 7:  ICFS32.FSI0[3:0] is a register that selects FRT to be connected to ICU-ch.2. 
Example 8:  ICFS32.FSI1[3:0] is a register that selects FRT to be connected to ICU-ch.3. 
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4. Registers of Multifunction Timer 
 
Examples 5 to 8 are examples of the individual notation that clearly identifies the correspondence between 
the control bit and the channel in the control registers by stating two channel numbers in the control register 
(ICFS). 
Example 9:  ICFS.FSI0[3:0] is a register  that selects FRT to be connected to ICU-ch.(0). 
Example 10:  ICFS.FSI1[3:0] is a register  that selects FRT to be connected to ICU-ch.(1). 
Examples 9 and 10 are examples of the common notation with parentheses that omits the channel numbers 
of the control register. What the description explains means that similar to Examples 5 to 8, repeated 
explanations are omitted by the common notation. 
It should be noted that wh ere the common notation is used in explan ation of each function block, as shown 
above, it must be converted into the individual notation for the relevant channel when it is read. 
Ta b l e  4 - 1  and Ta b l e  4 - 3  show the correspondence table between  the indivi
d
 ual notation and common 
notation. For the correspondence between the individual notation and common notation regarding register 
names, see the list of registers. 
Table 4-1 Individual Notation and Common Notation of OCU 
Channel Number 5 4 3 2 1 0 
Individualch.5 ch.4  ch.3 ch.2 ch.1 ch.0 Notation for explaining OCU operation 
Commonch.(1)ch.(0)ch.(1)ch.(0) ch.(1) ch.(0)
IndividualRT 5  RT 4   RT 3  RT 2  RT 1  RT 0  Notation of names of signals output from 
OCU 
CommonRT(1)RT(0)RT(1)RT(0) RT(1) RT(0)
 
Table 4-2 Individual Notation and Common Notation of WFG 
Channel Number 54 32 10 
Individual ch.54 ch.32  ch.10 Notation for explaining WFG operation 
CommonNo notation 
IndividualRT 5  RT 4   RT 3  RT 2  RT 1  RT 0  Names of signals input from OCU 
CommonRT(1)RT(0)RT(1)RT(0) RT(1) RT(0)
IndividualRTO 5RTO 4 RTO 3RTO 2  RTO 1  RTO 0Names of signals output from WFG 
CommonRTO(1)RTO(0)RTO(1)RTO(0) RTO(1) RTO(0)
IndividualCH10_PPG CH32_PPG  CH54_PPG Names of PPG input signals after selected 
to be input from PPG 
CommonCH_PPG 
Signal NameCH10_GATE  CH32_GATE CH54_GATE Names of GATE signals before selected to 
be output to PPG 
CommonCH_GATE 
 
Table 4-3 Individual Notation and Common Notation of ICU 
Channel Number 3 2 1 0 
Individualch.3 ch.2 ch.1 ch.0 Notation for explaining ICU operation 
Commonch.(1) ch.(0) ch.(1) ch.(0) 
IndividualIC3 IC2 IC1 IC0 Notation of names of ICU input signals 
CommonIC(1) IC(0) IC(1) IC(0) 
 
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4.2.  List of Registers of Multifunction Timer 
This section provides a list of the registers that exist in the multifunction timer unit. 
Ta b l e  4 - 4 shows a list of the registers that ex ist in the mult ifunction timer unit. 
The control registers of the multifunction timer unit are in the same configuration across the mounted 
channels. In this section, the operation of registers of the same function is explained using the common 
notation. The List of Registers states names in the individual notation and the common notation for each 
register. Replace the name in the common notation that appears in descriptions  with the name in the 
individual notation when reading the descriptions. 
Registers shown in the List of Registers refer to the  registers that exist in the Multifunction Timer 1 unit. A 
model containing more than one multifunction timer unit  has sets of the same registers for the number of 
the multifunction timer units. 
Table 4-4 List of Registers of Multifunction Timer Unit 
Block 
Name  Register 
Name 
(Individual  Notation)  Register Function 
Bit 
Width AccessSee  Register Name 
(Common Notation)
TCSA0  FRT ch.0 control register A 
TCSA1 FRT ch.1 control register A 
TCSA2 FRT ch.2 control register A  16
B, H 4.3.1 TCSA 
TCSB0  FRT ch.0 control register B 
TCSB1 FRT ch.1 control register B 
TCSB2 FRT ch.2 control register B  16
B, H 4.3.2 TCSB 
TCCP0  FRT ch.0 cycle setting register 
TCCP1 FRT ch.1 cycle setting register 
TCCP2 FRT ch.2 cycle setting register  16
H 4.3.3 TCCP 
TCDT0  FRT ch.0 count value register 
TCDT1 FRT ch.1 count value register 
FRT 
TCDT2  FRT ch.2 count value register  16
H 4.3.4 TCDT 
OCFS10  OCU ch.1, ch.0 connecting FRT select 
register 
OCFS32 OCU ch.3, ch.2 connecting FRT select 
register  B, H
OCFS54 
OCU ch.5, ch.4 connecting FRT select 
register  8 
B 4.3.5 OCFS 
OCSA10 
OCU ch.1, ch.0 control register A 
OCSA32 OCU ch.3, ch.2 control register A 
OCSA54 OCU ch.5, ch.4 control register A  8 B, H
4.3.6 OCSA 
OCSB10 OCU ch.1, ch.0 control register B 
OCSB32 OCU ch.3, ch.2 control register B 
OCSB54 OCU ch.5, ch.4 control register B  8 B, H
4.3.7 OCSB 
OCSC OCU ch.5 ~ ch.0 control register C  8 B 4.3.8 OCSC 
OCCP0  OCU ch.0 compare value store register  OCCP(0)
OCCP1 OCU ch.1 compare value store register  OCCP(1)
OCCP2 OCU ch.2 compare value store register  OCCP(0)
OCCP3 OCU ch.3 compare value store register  OCCP(1)
OCCP4 OCU ch.4 compare value store register  OCCP(0)
OCU 
OCCP5 OCU ch.5 compare value store register  16H 
4.3.9 OCCP 
OCCP(1)
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4. Registers of Multifunction Timer 
 
 Block 
Name  Register 
Name 
(Individual  Notation)  Register Function 
Bit 
Width Acces
s  See  Register Name 
(Common Notation)
WFSA10  WFG ch.10 control register A 
WFSA32 WFG ch.32 control register A 
WFSA54 WFG ch.54 control register A  16
H 4.3.10 WFSA 
WFTM10  WFG ch.10 timer value register 
WFTM32 WFG ch.32 timer value register 
WFG 
WFTM54 WFG ch.54 timer value register  16H 
4.3.11 WFTM 
NZCL NZCL control register  16H 4.3.12 NZCL NZCL 
WFIR Interrupt control register 16H  4.3.13 WFIR 
ICFS10 ICU ch.1, ch.0 connecting FRT select 
register 
ICFS32 ICU ch.3, ch.2 connecting FRT select 
register  8 B, H
4.3.14 ICFS 
ICSA10  ICU ch.1, ch.0 control register A 
ICSA32 ICU ch.3, ch.2 control register A  8 B, H
4.3.15 ICSA 
ICSB10  ICU ch.1, ch.0 control register B 
ICSB32 ICU ch.3, ch.2 control register B  8 B, H
4.3.16 ICSB 
ICCP0  ICU ch.0 capture value store register 
ICCP1 ICU ch.1 capture value store register 
ICCP2 ICU ch.2 capture value store register 
ICU 
ICCP3 ICU ch.3 capture value store register  16H 
4.3.17 ICCP 
ACSA ADCMP ch.2 to ch.0 control register A  16B, H 4.3.18 ACSA 
ACSB  ADCMP ch.2 to ch.0 control register B  8 B 4.3.19 ACSB 
ACCP0  ADCMP ch.0 compare value store 
ACCP1 ADCMP ch.1 compare value store 
ACCP2 ADCMP ch.2 compare value store  16
H 4.3.20 ACCP 
ACCPDN0  ADCMP ch.0 compare value store 
ACCPDN1 ADCMP ch.1 compare value store 
ADCMP 
ACCPDN2 ADCMP ch.2 compare value store  16H 
4.3.21 ACCPDN 
ATSA ATSA  ADC start trigger select register  16H 4.3.22 ATSA 
 
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4. Registers of Multifunction Timer 
 
4.3.  Details of Register Functions 
This section explains details of the registers that exist in the multifunction timer unit. 
4.3.1  FRT Control Register A (TCSA)  
4.3.2   FRT Control Register B (TCSB)  
4.3.3   FRT Cycle Setting Register (TCCP)  
4.3.4   FRT Count Value Register (TCDT)  
4.3.5   OCU Connecting FRT Select Register (OCFS)  
4.3.6   OCU Control Register A (OCSA)  
4.3.7   OCU Control Register B (OCSB)  
4.3.8   OCU Control Register C (OCSC)  
4.3.9   OCU Compare Value Store Register (OCCP)  
4.3.10  WFG Control Register A (WFSA)  
4.3.11  WFG Timer Value Register (WFTM)  
4.3.12  NZCL Control Register (NZCL)  
4.3.13  WFG Interrupt Control Register (WFIR)  
4.3.14  ICU Connecting FRT Select Register (ICFS)  
4.3.15  ICU Control Register A (ICSA)  
4.3.16  ICU Control Register B (ICSB)  
4.3.17  ICU Capture value store register (ICCP)  
4.3.18  ADCMP Control Register A (ACSA) 
4.3.19  ADCMP Control Register B (ACSB) 
4.3.20  ADCMP Compare Value Store Register (ACCP) 
4.3.21  ADCMP Compare Value Store Register,  Down-cou
nt Dire
 ction Only (ACCPDN) 
4.3.22  ADC Start Trigger Sel ect Register (ATSA) 
 
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4. Registers of Multifunction Timer 
 
4.3.1. FRT Control Register A (TCSA) 
TCSA is a 16-bit register that controls FRT. 
Each mounted channel has three registers: TCSA0, TCSA1 and TCSA2. 
TCSA0 controls FRT-ch.0. 
TCSA1 controls FRT-ch.1. 
TCSA2 controls FRT-ch.2. 
 Configuration of Register 
Bit  15 14 13  12 11 10  9 8 
Field ECKE  IRQZF IRQZE  Reserved  ICLR ICRE 
Attribute  R/W R/W R/W  - R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
           
Bit  7 6 5  4 3 2 1 0 
Field BFE  STOP MODE  SCLR  CLK[3:0] 
Attribute R/W R/W R/W  W R/W 
Initial value 0 1 0  0 0 0 0 0 
 
  Functions of Register 
[bit3:0] TCSA.CLK[3:0] 
Process Value  Function 
0000 Sets FRT’s count clock cycle to the same value as PCLK. 
0001  Sets FRT’s count clock cycle to PCLK multiplied by 2. 
0010 Sets FRT’s count clock cycle to PCLK multiplied by 4. 
0011 Sets FRT’s count clock cycle to PCLK multiplied by 8. 
0100  Sets FRT’s count clock cycle to PCLK multiplied by 16. 
0101 Sets FRT’s count clock cycle to PCLK multiplied by 32. 
0110 Sets FRT’s count clock cycle to PCLK multiplied by 64. 
0111 Sets FRT’s count clock cycle to PCLK multiplied by 128. 
1000  Sets FRT’s count clock cycle to PCLK multiplied by 256. 
Write 
Other than 
above  Setting prohibited 
Read 
- Reads the register setting. 
 
TCSA.CLK[3:0] is a register that sets the count cl ock cycle of FRT counter (16-bit Up/Down counter). 
Change the setting of this register while FRT is stopping. 
As for FRT count clock, either the PCLK in LSI which is divided by the pre-scaler or an external clock 
input can be selected for use. As this register se tting is the setting for the pre-scaler, its value has no 
meaning if an external clock input is selected. 
FRT’s count clock cycle is determined based on the PCLK cycle and the clock division ratio set by this 
register. 
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The following table shows examples of CLK[3:0] settings and FRT count clock cycles. 
FRT Count Clock Cycle 
CLK[3:0] Clock 
Ratio  PCLK=25ns 
(40MHz)  PCLK=33.3ns 
(33MHz)  PCLK=50ns 
(25MHz) 
0000  1  25ns 30ns 50ns 
0001 2  50ns 61ns 100ns 
0010 4  100ns 121ns 200ns 
0011 8  200ns 242ns 400ns 
0100 16  400ns 485ns 800ns 
0101 32  800ns 970ns  1.6μs 
0110 64  1.6μs 1.9 μs 3.2 μs 
0111 128  3.2μs 3.9 μs 6.4 μs 
1000 256  6.4μs 7.8 μs 12.8 μs 
 
[bit4] TCSA.SCLR 
Process Value  Function 
0 Cancels FRT operation state initialization request. Write 
1 Issues FRT operation state initialization request. 
Read - 0 is always read. 
 
TCSA.SCLR is a register that reque sts FRT operation state initialization. 
There are two ways to use this register, as described below. 
1.  When stopping FRT counter 
Write 1 to issue an initialization request for FRT’s operation state when stopping FRT counter. 
2.  When clearing FRT counter through clock synchronization 
Write 1 to issue a request to clear FRT’s count value to 0x0000 through synchronization when 
operating FRT in Up-count mode. 
For information about how to use this register, see the section regarding TCSA.STOP. 
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4. Registers of Multifunction Timer 
 
[bit5] TCSA.MODE 
Process Value Function 
0 Sets FRT’s count mode to Up-count mode. Write 
1 Sets FRT’s count mode to Up/Down-count mode. 
Read - Read the register setting. 
 
TCSA.MODE is a register that selects FRT’s count mode. 
Change the setting of this register while FRT is stopping. 
In Up-count mode, FRT performs the following operation. 
FRT’s counter starts Up-count operation from 0x0000 . After up-counting to the value set by the TCCP 
register, the value of the counter becomes 0x0000.  Then, the Up-count operation is repeated. FRT’s count 
cycle is (TCCP+1) x Count clock cycle.   
Change in the value of FRT’s counter is shown below. 
0x0000 (Zero value)  
0x0001   
0x0002   ・  
  
・  
(Up-count)  FRT’s count cycle 
・  
  
TCCP-2    
TCCP-1    
TCCP (Peak value)   
0x0000 (Zero value)   
0x0001    
0x0002    
・  
  
・  
(Up-count)  FRT’s count cycle 
・  
  
TCCP-2    
TCCP-1    
TCCP  (Peak value)   
0x0000 (Zero value)    
0x0001     
 
 
TCSA.MODE=0 Up count mode
FRT count 
0x0000
PEAK (=TCCP)
time 
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4. Registers of Multifunction Timer 
 
In Up/Down-count mode, FRT performs the following operation. 
FRT’s counter starts Up-count operation from 0x0000. After up-counting to the value set by the TCCP 
register, it starts Down-count operation. When it return s to 0x0000, it starts up-counting again and repeats 
the count operation. FRT’s count cycle is (TCCP) x 2 x Count clock cycle. 
Change in the value of FRT’s counter is shown below. 
0x0000 (Zero value)  
0x0001   
0x0002   ・  
  
・  
(Up-count)  
・  
  
TCCP-2   
TCCP-1    TCCP (Peak value) FRT’s count cycle 
TCCP-1   
TCCP-2   
・ 
  
・  
(Down-count)  
・  
  
0x0002   
0x0001   
0x0000 (Zero value)  
0x0001   
0x0002    ・  
  
・  
(Up-count) FRT’s count cycle 
・  
  
TCCP-2   
TCCP-1    TCCP (Peak value)  
TCCP-1   
TCCP-2   
・ 
  
・  
(Down-count)  
・  
  
0x0002   
0x0001   
0x0000 (Zero value)   
0x0001    
 
 
TCSA.MODE=1 Up-down count mode
FRT count 
0x0000
time
PEAK (=TCCP)
 
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4. Registers of Multifunction Timer 
 
[bit6] TCSA.STOP 
Process Value Function 
0 Puts FRT in operating state. Write 
1 Puts FRT in stopping state. 
Read - Reads the register setting 
 
TCSA.STOP is a register that controls  the start and stop of FRT’s operation. 
This register is used in the combina tion with TCSA.SCLR, as shown below. 
1.  When starting FRT’s counter operation:   
When 0 is written to TCSA.STOP and TCSA.SCLR while FRT’s count operation is stopped, FRT 
starts counting. 
2.  When clearing the count value of FRT’s counter to 0x0000 through synchronization in Up-count 
mode:  
If 0 is written to TCSA.STOP and 1 is written to TCSA.SCLR during FRT’s count operation in 
Up-count mode, FRT’s count value is cleared to 0x0000 in FRT’s next count clock. If 0 is written to 
TCSA.SCLR before the counter is cleared, the counter  clear request is cancelled and the counter value is 
not cleared. Do not write TCSA.SCLR=0 until it can be  checked that the counter value is cleared. This 
operation cannot be performed in Up/Down-count mode. 
3.  When stopping the operation of FRT’s counter:   
If 1 is written to TCSA.STOP and TCSA.SCLR during FRT’s count operation, FRT stops the count 
operation. In some cases, FRT’s counter value is  not initialized to 0x0000 even after FRT stops, 
depending on the state of FRT’s count clock. Always write 0x0000 to TCDT afterwards to clear FRT’s 
counter value to 0x0000. 
To rewrite to another register in the same addr ess area during FRT’s count operation, write 0 to 
TCSA.STOP and TCSA.SCLR. 
To rewrite to another register in the same address area while FRT’s count operation is stopped, write 1 to 
TCSA.STOP and 0 to TCSA.SCLR. 
 
Figure 4-1 FRT Counter Start, Clear and Stop (Up-count Mode) 
 
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FRT counter start , clear, stop ( up-count mode)
0x0000 
PEAK (=T
CCP) 
FRT count 
time
  Start FRT (ST O
 P=0, SCLR=0 )
Clear FRT (STOP=0, SCLR=1 )  
Stop FRT (STOP=1, SCLR=1, TCDT=0x0000 )   
 
 
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