Fujitsu Series 3 Manual

							 
4. Registers of Multifunction Timer 
 
4.3.21.  ADCMP Compare Value Store Register, Down-count Direction Only (ACCPDN) 
ACCPDN is a 16-bit register that specifies the timing of starting AD conversion at ADCMP as 
the compare value of the FRT count value. 
Each mounted channel has three registers: ACCPDN0, ACCPDN1 and ACCPDN2. 
ACCPDN0 stores the compare value of ADCMP ch0. 
ACCPDN1 stores the compare value of ADCMP ch1. 
ACCPDN2 stores the compare value of ADCMP ch2. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
 
Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field ACCPDN[15:0] 
Attribute R/W 
Initial  Va l u e   0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
  Functions of Register 
[bit15:0] ACCPDN.ACCPDN[15:0] 
Process Function 
Write  Specifies the timing of starting AD conver
sion. The value is written to the ACCPDN 
buffer register. 
Read  Reads the value in the ACCPDN register 
(not the value in the ACCPDN buffer 
register). 
  ACCPDN is a register that specifies  the timing of starting AD conversion. 
Each specifies the timing of starting AD conversion, only when the setting values of ACSA.SEL0[1:0], 
ACSA.SEL1[1:0], ACSA.SEL2[1:0]  is 11. 
When data is written to this address area, the data is fi rst stored in the buffer register. And then, the data is 
transferred from the buffer register to the ACCP register under the following conditions. 
When the buffer function is disabled: 
Data is transferred immediately after  it is written to the buffer register. 
When the buffer function is enabled and the tran sfer upon Zero value detection is enabled: 
Data is transferred, when FRT’s counter is stopped or when FRT’s count value has reached 0x0000. 
When the buffer function is enabled and the tran sfer upon Peak value detection is enabled: 
Data is transferred, when FRT’s counter is stopped or when FRT’s count value has matched the TCCP 
value. 
The enabling/disabling of the buffer function and the timin g of data transfer are determined by the value of 
the corresponding register ACSB.BDIS0, BDIS1, BDIS2, BTS0, BDIS1, or BDIS2. 
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During FRT’s count operation, the timing of starting AD conversion can be changed by rewriting to this 
register. When the buffer function is disabled, the written value can be immediately reflected on the 
ACCPDN register. When the buffer function is enable d, the settings in the ACCPDN register for multiple 
channels can be synchronized.   
If data is read from this address area, the value in the ACCPDN register is read, rather than the value in the 
buffer register. Therefore, it should  be noted that no bit can be rewritten by RMW access to this address area 
when the buffer function is enabled. 
 
  AD conversi o

n cannot be started by writing 0x0000 to this register. 
   If the bu f

fer function of ACCPDN register is to be used, use FRT-ch.0 for FRT to be connected. 
 
 
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4. Registers of Multifunction Timer 
 
4.3.22.  ADC Start Trigger Select Register (ATSA) 
ATSA is a 16-bit register that selects ADC’s start signal which is output from MFT. 
This register is used to select a start trigger for ADCunit0, unit1 and unit2. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
Bit  15 14 13  12 11 10  9 8 
Field  Reserved  AD2P AD1P AD0P 
Attribute - R/W R/W R/W 
Initial Value  - 0 0 0 0  0 0 
           
Bit  7 6 5  4 3 2 1 0 
Field  Reserved  AD2S AD1S AD0S 
Attribute - R/W R/W R/W 
Initial Value  - 0 0 0 0  0 0 
 Functions of Register 
[bit1:0] ATSA.AD0S[1:0] 
Process Value  Function 
00 Selects the start signal of ADCMP ch.0 as ADC unit0 scan conversion start signal.
01 Selects the OR signal of FRTch.0 to 
ch.2 start signal as ADC unit0 scan 
conversion start signal. Write 
Other than above  Setting prohibited 
Read 
- Reads the register setting. 
 
[bit3:2] ATSA.AD1S[1:0] 
Process Value  Function 
00 Selects the start signal of ADCMP ch.1 as ADC unit1 scan conversion start signal.
01 Selects the OR signal of FRTch.0 to 
ch.2 start signal as ADC unit1 scan 
conversion start signal. Write 
Other than above  Setting prohibited 
Read 
- Reads the register setting. 
 
[bit5:4] ATSA.AD2S[1:0] 
Process Value  Function 
00 Selects the start signal of ADCMP ch.2 as ADC unit2 scan conversion start signal.
01 Selects the OR signal of FRTch.0 to 
ch.2 start signal as ADC unit2 scan 
conversion start signal. Write 
Other than above  Setting prohibited 
Read 
- Reads the register setting. 
 
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ATSA.AD0S[1:0] is a register that selects the start signal to be used to start the scan conversion of ADC unit0. 
ATSA.AD1S[1:0] is a register that selects the start signal to be used to start the scan conversion of ADC unit1. 
ATSA.AD2S[1:0] is a register that selects the start signal to be used to start the scan conversion of ADC unit2. 
The starting method used for ADC’s scan conversion start signal that is output from MFT can be selected 
from starting by ADCMP or starting by FRTch.0 to ch.2. The above is selected by the setting in this register. 
Change the setting of this register, when the operation of ADCMP to be connected is disabled. 
For models containing multiple MFT’s, the ADC scan conversion start signal from MFT undergoes logic 
OR for each MFT unit, and then it is connected to ADC. For details, see the chapter A/D Converter. 
[bit7:6] Reserved 
Process Function 
Write  The written value is ignored. 
Read An undefined value is read. 
 
[bit9:8] ATSA.AD0P[1:0] 
Process Value  Function 
00 Selects the start signal of ADCMP ch.0 as ADC unit0 priority conversion 
start signal. 
01 Selects the logic OR signal of FRTch.0 to ch.2 as ADC unit0 priority 
conversion start signal. Write 
Other than above  Setting prohibited 
Read 
- Reads the register setting. 
 
[bit11:10] ATSA.AD1P[1:0] 
Process Value  Function 
00 Selects the start signal of ADCMP ch.1 as ADC unit1 priority conversion 
start signal. 
01 Selects the logic OR signal of FRTch.0 to ch.2 as ADC unit1 priority 
conversion start signal. Write 
Other than above  Setting prohibited 
Read 
- Reads the register setting. 
 
[bit13:12] ATSA.AD2P[1:0] 
Process Value  Function 
00 Selects the start signal of ADCMP ch.2 as ADC unit2 priority conversion 
start signal. 
01 Selects the logic OR signal of FRTch.0 to ch.2 as ADC unit2 priority 
conversion start signal. Write 
Other than above  Setting prohibited 
Read 
- Reads the register setting. 
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4. Registers of Multifunction Timer 
 
ATSA.AD0P[1:0] is a register that selects the start signal to be us ed to start priority conversion of ADC 
unit0. 
ATSA.AD1P[1:0] is a register  that selects the start signal to be us ed to start priority conversion of ADC 
unit1. 
ATSA.AD2P[1:0] is a register  that selects the start signal to be us ed to start priority conversion of ADC 
unit2. 
The starting method used for ADC’s priority conversion st art signal that is output from MFT can be selected 
from starting by ADCMP or starting by FRTch.0 to ch.2. The above is selected by the setting in this register. 
Change the setting of this register, when the operation of ADCMP to be connected is disabled. 
For models containing multiple MFT’s, the ADC priority  conversion start signal from MFT undergoes logic 
OR for each MFT unit, and then it is connected to  ADC. For details, see the chapter A/D Converter. 
[bit15:14] Reserved 
Process Function 
Write  The written value is ignored. 
Read An undefined value is read. 
 
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4. Registers of Multifunction Timer 
 
4.4.  Details of OCU Output Waveform 
This section provides details of the output waveform of the RT output signal in each mode of 
OCU. 
 List of OCU Operation Modes 
The operation modes of the OCU are select ed by the following register settings. Table 4-6  shows a list of 
register setting values an
d the operatio n modes of OCU-ch.(0) and OCU-ch.(1). 
Table 4-6 Register Setting Values and the Operation Modes of OCU-ch.(0) and OCU-ch.(1) 
Register Setting  Operation Mode Selected 
TCSA. 
MODE 
-Ch.(1)  (*1)  TCSA. 
MODE 
-Ch.(0)  (*2)  OCSB. 
CMOD 
(*3)  OCSC. 
MOD 
(*4)  CH(1) 
Operation Mode  CH(0) 
Operation Mode 
0 0 0  00 Up-count mode (1-cha nge) Up-count mode (1-change) 
0 0 1  00 Up-count mode (2-cha nge) Up-count mode (1-change) 
0 1 0  01 Up-count mode (1-change)  Up/Down-count mode   
(Active High) 
1 0 0 
10 Up/Down-count mode   
(Active High)  Up-count mode (1-change) 
1 0 1 
10 Up/Down-count mode   
(Active Low)  Up-count mode (1-change) 
1 1 0 
11 Up/Down-count mode   
(Active High)  Up/Down-count mode   
(Active High) 
1 1 1 
11 Up/Down-count mode   
(Active Low)  Up/Down-count mode   
(Active Low) 
*1  TCSA.MODE-ch.(1) indicates the 
TCSA.MODE value of FRT to be conn ected to OCU-ch.(1) selected by 
the OCFS register. 
*2  TCSA.MODE-ch.(0) indicates the  TCSA.MODE value of FRT to be conn ected to OCU-ch.(0) selected by 
the OCFS register. 
*3  OCSB.CMOD indicates the OCSB10.CMOD value for ch.1-ch.0. It indicates the OCSB32.CMOD value for  ch.3-ch.2. It indicates the OCSB54.CMOD value for ch.5-ch.4. 
*4  OCSC.MOD indicates the  OCSC.MOD[1:0] value for ch.1-ch.0. It indicates the OCSC.MOD[3:2] value for 
ch.3-ch.2. It indicates the OCSC.MOD[5:4] value for ch.5-ch.4. 
*5  OCSB.CMOD and OCSC.MOD[5:0] cannot be used in combinations other than listed above. 
*6  OCU ch.(0) cannot use Up-count mode (2-change). 
  List of Changes of the RT(0) and RT (1) Signals in OCU Operation Modes 
When each channel of OCU is in the state of Opera tion enabled, if the FRT counter value matches the 
OCCP register value, the output signal level changes. In addition, the changes of the output signal level are 
determined by the operation mode of OCU, the value of OCCP, and the count state of FRT.  Ta b l e  4 - 7 shows 
a list o f OCU-ch
.(0) 

operation modes, regi ster settings and RT(0) signal outputs.  Ta b l e  4 - 8 shows a list of 
OCU-ch.(1) operation mo d

es, register settings and RT(1) signal outputs. 
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Table 4-7 Details of OCU-ch.(0) Operation and RT(0) Signal Outputs 
OCCP(0) value 
Other than 0x0000 & 0xFFFF   Name of Operation Mode 0x0000 0xFFFF 
Up Peak Down 
Up-count mode (1-change) M:Rev 
U:No M:Rev 
U:No M:Rev 
U:No  M:Rev 
U:No 
- 
Up/Down-count mode (Active High) All-Act All-Ina M:Act 
U:No  M:Ina 
U:No 
Up/Down-count mode (Active Low) All-Act All-Ina M:Act 
U:No M:No 
U:No 
(*7) 
M:Ina 
U:No 
 
Table 4-8 Details of OCU-ch.(1) Operation and RT(1) Signal 
OCCP(1) value 
Other than 0x0000, 0xFFFF Name of Operation Mode 
0x0000 0xFFFF 
Up Peak Down  OCCP(0) 
value 
Up-count mode (1-change) M:Rev 
U:No  M:Rev 
U:No M:Rev 
U:No  M:Rev 
U:No 
- 
Up-count mode (2-change) M:Rev 
U:No M:Rev 
U:No M:Rev 
U:No  M:Rev 
U:No - 
M:Rev 
U:No 
Up/Down-count mode (Active High) All-Act All-Ina M:Act 
U:No  M:Ina 
U:No 
- 
Up/Down-count mode (Active Low) All-Act All-Ina M:Act 
U:No M:No 
U:No 
(*7) 
M:Ina 
U:No - 
 
* Meanings of symbols in 
Ta b l e  4 - 7 and Table 4-8 
Up  : Operation  wh

en FRT is up-counting 
Peak  : Operation when FRT’s count value is the Peak value (=TCCP value) 
Down  : Operation when FRT is down-counting 
 
M  : Operation when FRT’s count value matches the OCCP value 
U  : Operation when FRT’s count value does not match the OCCP value 
 
Rev  : Change of the output signal level to the Reversed level. 
Act    : Change of the output signal level to the Active level. No change, if the previous output level was  already Active. 
Ina  : Change of the output signal level to the Inactive level. No change, if the previous output level  was already Inactive. 
No  : No change of the output signal level. 
 
All-Act  : Change of the output signal level to the Active level, while the OCCP value is that value. 
All-Ina  : Change of the output signal level to the Inactive level, while the OCCP value is that value. 
 
*7  In Up/Down count mode, if the peak FRT count value matches OCCP value, the RT(0) and RT(1) output  signals do not change, and the OCSA.IOP0 and IOP1 fl ags are not set. 
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4. Registers of Multifunction Timer 
 
 Up-count Mode (1-change) 
When Up-count mode (1-change) is selected, the following operation applies. 
Regardless of FRT’s count state, the output level of the RT(0) signal is reversed when FRT’s count value 
matches OCCP(0). 
Regardless of FRT’s count state, the output level of the RT(1) signal is reversed when FRT’s count value 
matches OCCP(1). 
In this mode, OCU-ch.(0) and ch.(1) can operate inde pendently from each other. 
Figure 4-14  shows an example of operation waveform when OCU-ch.0 is in Up-count mode (1-change). 
Th is figure illustrates the state in
 

which the buffer function of the OCCP0  register is disabled. 
Figure 4-14 Example of Operation Waveform in OCU Up-count Mode (1-change) 
 
OCCP0 reg.FRT count 
0x0000
Peak (=TCCP)
Value0
Value1
RT0 output
Value2
OCCP0 Buf.reg.
Value3 Value4
Value3Value1Value4Value3Value2Value3PeakValue0
Value3Value1Value4Value3Value2Value3PeakValue0
OCU wave form: Example of up-count mode (ch.0, 1change, OCSA.BDIS0=1)
  
 
 
A n

ote on Up-count mode (1-change) is as follows: 
   If a value lar g

er than the Peak value of FRT’s counter (e.g. Value0 in  Figure 4-14) is set to OCCP, the 
output does n o

t change. 
 
 
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4. Registers of Multifunction Timer 
 
 Up-count Mode (2-change) 
When Up-count mode (2-change) is selected, the following operation applies. 
Regardless of FRT’s count state, the output level of the RT(1) signal is reversed when FRT’s count value 
matches OCCP(0) or OCCP(1). 
This mode can be used only by OCU ch.(1), not by ch.(0). Also, as OCU-ch.(0) and ch.(1) perform 
interlocked operation, they cannot operate independently from each other. If 2-change mode is selected for 
OCU-ch(1), OCU-ch.(0) operates in 1-change mode to perform the operation that  changes according to the 
OCCP(0) value. 
Figure 4-15 Example 1 of Operation Waveform in OCU Up-count Mode (2-change) 
 
OCU wave form: Example1 of up-count mode (c h.1, 2change, OCSA.BDIS0,1=00, OCSB.BTS0,1=00
OCCP1 reg.FRT count 
0x0000
Peak (=TCCP)
Value0
Value1
RT1 output
Value2
OCCP0 Buf.reg.
Value3 Value4
Value3Value3Value40x0000Value3
OCCP1 Buf.reg.Value1Value2PeakValue3Value3
Value1Value2Value3Peak
OCCP0 reg.
Value3Value40x0000Value3Value3
Value3
▼
★
  
 
Figure 4-16 Example 2 of Operation Waveform in OCU Up-count Mode (2-change) 
 
OCCP1 reg.FRT count 
0x0000
Peak (=TCCP)
Value0
Value1
RT1 output
Value2
OCCP0 Buf.reg.
Value3
Value4
OCCP1 Buf.reg.
Value1Value2
OCCP0 reg.
value4Value3
▼
Value3Value4
Value1Value2
★
Value30x0000Value3
PeakValue3Value3
Value3Peak
Value30x0000Value3
Value3
OCU wave form: Example2 of up-count mode (ch.1, 2change, OCSA.BDIS0,1=00, OCSB.BTS0,1=11
 
 
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4. Registers of Multifunction Timer 
 
Figure 4-15 shows Example 1 of the operation waveform when OCU-ch.1 is in Up-count mode (2-change). 
This figure is based on  the conditions that the buffer  function of the OCCP1 register is enabled and Zero 
value transfer is set. 
Figure 4-16  shows Example 2 of the operation waveform when OCU-ch.1 is in Up-count mode (2-change). 
Th is figure is based on

 the conditions that the buffer  function of the OCCP1 register is enabled and Peak 
value transfer is set. 
Due to the difference in the timi ng of OCCP data transfer between  Figure 4-15 and Figure 4-16, they 
o perate dif

ferently when the Peak value is set to OCCP1. 
In the case of  Figure 4-15, data is transferred from the OCCP1 buffer register to the OCCP1 register, when 
FR T’s counter 
v

alue is 0x0000. The output level is reversed at the timing indicated by  , under the 
condition: OCCP1=Peak value. 
In the case of  Figure 4-16, data is transferred from the OCCP1 buffer register to the OCCP1 register, when 
FR T’s counter value reac

hes the Peak value. As the  register values are compared immediately after the 
transfer, the output level is reversed at the timing indicated by  , under the condition: OCCP1=Peak value. 
 
Notes

 on Up-count mode (2-change) are as follows: 
   If a value lar g

er than the Peak value of FRT’s counter (e.g. Value0 in  Figure 4-15) is set to OCCP, the 
output does n o

t change. 
   If the same value is set to OCCP(0) and OCCP(1), the  output level is reversed at the timing indicated by 
 , as shown in  Figure 4-15 and Figure 4-16 . 
   It is n ecessary to set the op
eratio

n enable  flags of both OCSA.CST0 and OCSA.CST1. 
   OCSA.IOP0 is set when FRT’s count value matches OCCP(0). 
   OCSA.IOP1 is set when FRT’s count value matches OCCP(1). 
   It is necessary to apply the same settings for which FRT is to be connected; whether to enable or disable 
the buffer function; and the transfer timing, for both OCU ch.(0) and ch.(1). 
 
 
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