Fujitsu Series 3 Manual
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3. CSIO (Clock Sync Serial Interface) operations Continuous data transmit or receive waiting If anything other than (ESCR:WT1, ESCR.WT0)=(0, 0) is set for the continuous data transmission or reception, a wait is inserted between frames. - ESCR.WT1=0, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte1bit - ESCR.WT1=1, ESCR.WT0=0 (in master mode operation) SCK 1Byte 2Byte2bit - ESCR.WT1=1, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte3bit TDRE TDRE TDRE FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 865 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Slave mode operation (Set SCR:MS=1 and SMR:SCKE=0.) Data transmission 1. If serial data output is enabled (SMR:SOE=1) and data transmission is enabled (SCR:TXE=1) and when the transmit data is written in the TD R, the SSR:TDRE bit is set to 0. This causes the transmit data to be output in synchronization with a falling edge of the serial clock (SCK) input. 2. When the transmit data of the first bit is output, the SSR:TDRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interru pt request is output. During this time, the transmit data of the 2nd byte can be written in the register. Data reception 1. If the serial data output is disabled (SMR:SOE =0) and data reception is enabled (SCR:RXE=1), the receive data is sampled at a rising edge of serial clock (SCK) input. 2. When the last bit is received, th e SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive data (RDR) can be read during this time. 3. When the receive data (RDR) is read, the SSR:RDRF bit is cleared to 0. Data transmission and reception 1. To perform data transmission and reception simultaneously, enable the serial data output (SMR:SOE=1) and enable the data transmission and reception (SCR:TXE, RXE=1). 2. When the transmit data is written in the TDR, the SSR:TDRE bit is set to 0 and the transmit data is output in synchronization with a falling edge of the serial clock (SCK) input. When the transmit data of the first bit is output, the SSR:TDRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. 3. The receive data is sampled at a rising edge of the se rial clock (SCK) input. When the last bit of receive data is received, the SSR:RDRF bit is set to 1. If the receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive da ta (RDR) can be read during this time. When the receive data is read, the SSR:R DRF bit is cleared to 0. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 866 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations 3.2. Normal transfer (II) Features Item Description 1 Serial clock (SCK) signal detect level LOW 2 Transmit data output timing SCK signal rising edge 3 Receive data sampling SCK signal falling edge 4 Data length 5 to 9 bits Register settings The register values required for normal data transfer (II) are listed on the table below. Table 3-2 Normal transfer (II) register settings Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 09 Bit 08 Bit 07 Bit 06 Bit 05Bit 04 Bit 03 Bit 02 Bit 01Bit 00 UPCL MS SPIRIE TIE TBIE RXETXEMD2 MD1 MD0WUCR SCINV BDS SCKE SOESCR/ SMR 0 1/0 0 * * * * * 0 1 0 0 1 * 1/0 * REC - - - ORE RDRF TDRE TBISOP - - WT1WT0 L2 L1 L0SSR/ ESCR 0 - - - - - - - 0 - - * * * * * D8D7D6 D5 D4 D3 D2 D1 D0TDR/ RDR * * * * * * * * * - B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0BGR1/ BGR0 - * * * * * * * * * * * * * * * 1 : Set to 1. 0 : Set to 0. * : User-dependent values The ab ove bit setting (1/0) varies depending on the master or slave mode operation. Set as follows. During m a ster mode operation: SCR:MS=0, SMR:SCKE=1 During slave mode operation: SCR:MS=1, SMR:SCKE=0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 867 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Normal transfer (II) timing chart Data transmission SCK SOUT TDR RW TXE Data reception SIN RXE Sampling RDRF TDRE Signal detect level RDR RD D 7 D0 D 7 D 1 D2 D3 D 4 D5 D6 D0 D1 D2D3 D4 D5 D6 D7 D0 D7 D 1 D 2 D3 D 4 D5 D6 D0 D1 D2 D3 D4 D5 D6 1st byte 2nd byte * A D7 val ue if SCR:MS=1 HIGH if SCR:MS=0 * A : FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 868 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Master mode operation (Set SCR:MS=0 and SMR:SCKE=1.) Data transmission 1. If serial data output is enabled (SMR:SOE=1), da ta transmission is enabled (SCR:TXE=1) and data reception is disabled (SCR:RXE=0), and when the transmit data is written in the TDR, the SSR:TDRE bit is set to 0. This causes the transmit data to be output in synchronization with a rising edge of the serial clock (SCK) output. 2. When the transmit data of the first bit is output, the SSR:TDRE bit is set to 1. Therefore, if the transmit interrupt is enabled (SCR:TI E=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. Data reception 1. If the serial data output is disabled (SMR:SOE=0), data transmission is enabled (SCR:TXE=1) and data reception is enabled (SCR:RXE=1), and when a dummy da ta is written in the TDR, the receive data is sampled at a rising edge of serial clock (SCK) output. 2. When the last bit is received, th e SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1) during this time, a r eceive interrupt request is output. The receive data (RDR) can be read during this time. 3. When the receive data (RDR) is read, the SSR:RDRF bit is cleared to 0. To perform data reception only, write a dummy data in the TDR so t hat the serial clock (SCK) is output. If the FIFO transmission and reception are enabled, th e serial clocks (SCK) for the preset number of frames are output when the transmit fra mes are set in the FBYTE register. Data transmission and reception 1. To perform data transmission and reception simultaneously, enable the serial data output (SMR:SOE=1) and enable the data transmission and reception (SCR:TXE, RXE=1). 2. When the transmit data is written in the TDR, the SSR:TDRE bit is set to 0 and the transmit data is output in synchronization with a rising edge of the serial clock (SCK) output. When the transmit data of the first bit is output, the SSR:TDRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. 3. The receive data is sampled at a falling edge of th e serial clock (SCK) output. When the last bit of receive data is received, the SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive da ta (RDR) can be read during this time. When the receive data is read, the SSR:R DRF bit is cleared to 0. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 869 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Continuous data transmit or receive waiting If anything other than (ESCR:WT1, ESCR.WT0)=(0, 0) is set for the continuous data transmission or reception, a wait is inserted between frames. - ESCR.WT1=0, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte1bit - ESCR.WT1=1, ESCR.WT0=0 (in master mode operation) SCK 1Byte 2Byte2bit - ESCR.WT1=1, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte3bit TDRE TDRE TDRE FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 870 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Slave mode operation (Set SCR:MS=1 and SMR:SCKE=0.) Data transmission 1. If serial data output is enabled (SMR:SOE=1) and data transmission is enabled (SCR:TXE=1) and when the transmit data is written in the TD R, the SSR:TDRE bit is set to 0. This causes the transmit data to be output in synchronization with a rising edge of the serial clock (SCK) input. 2. When the transmit data of the first bit is output, the SSR:TDRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interru pt request is output. During this time, the transmit data of the 2nd byte can be written in the register. Data reception 1. If the serial data output is disabled (SMR:SOE =0) and data reception is enabled (SCR:RXE=1), the receive data is sampled at a falling edge of serial clock (SCK) input. 2. When the last bit is received, th e SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive data (RDR) can be read during this time. 3. When the receive data (RDR) is read, the SSR:RDRF bit is cleared to 0. Data transmission and reception 1. To perform data transmission and reception simultaneously, enable the serial data output (SMR:SOE=1) and enable the data transmission and reception (SCR:TXE, RXE=1). 2. When the transmit data is written in the TDR, the SSR:TDRE bit is set to 0 and the transmit data is output in synchronization with a rising edge of the serial clock (SCK) input. When the transmit data of the first bit is output, the SSR:TDRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. 3. The receive data is sampled at a falling edge of the se rial clock (SCK) input. When the last bit of receive data is received, the SSR:RDRF bit is set to 1. If the receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive da ta (RDR) can be read during this time. When the receive data is read, the SSR:R DRF bit is cleared to 0. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 871 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations 3.3. SPI transfer (I) Features Item Description 1 Serial clock (SCK) signal detect level HIGH 2 Transmit data output timing SCK signal rising edge 3 Receive data sampling SCK signal falling edge 4 Data length 5 to 9 bits Register settings The register values required for SPI data transfer (I) are listed on the table below. Table 3-3 SPI transfer (I) register settings Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 09 Bit 08 Bit 07 Bit 06 Bit 05Bit 04 Bit 03 Bit 02 Bit 01Bit 00 UPCL MS SPIRIE TIE TBIE RXETXEMD2 MD1 MD0WUCR SCINV BDS SCKE SOESCR/ SMR 0 1/0 1 * * * * * 0 1 0 0 0 * 1/0 * REC - - - ORE RDRF TDRE TBISOP - - WT1WT0 L2 L1 L0SSR/ ESCR 0 - - - - - - - 0 - - * * * * * D8D7 D6 D5 D4 D3 D2 D1 D0TDR/ RDR * * * * * * * * * - B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0BGR1/ BGR0 - * * * * * * * * * * * * * * * 1 : Set to 1. 0 : Set to 0. * : User-dependent values The ab ove bit setting (1/0) varies depending on the master or slave mode operation. Set as follows. During m a ster mode operation: SCR:MS=0, SMR:SCKE=1 During slave mode operation: SCR:MS=1, SMR:SCKE=0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 872 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations SPI transfer (I) timing chart *B Data transmission 1st byte 2nd byte *A D7 D0D7 D1D2 D3D4 D5D6D0 D1D2D3D4 D5 D6 D7 D0 D7 D1D2 D3 D4 D5D6 D0D1D2D3 D4 D5D6 SOUT SC K TDRE TDR RW TXE Data reception SIN Sampling RDRF RDR RD RXE * A : During slave mode transmission(MS=1, SOE=1), 4 machine cycles or more time is required after writing data in the TDR . * B : HIGH if SCR:MS=0 D0 of the 3rd byte if SCR:MS=1 and TDRE is LOW HIGH if SCR:MS=1 and TDRE is HIGH FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 873 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Master mode operation (Set SCR:MS=0 and SMR:SCKE=1.) Data transmission 1. If serial data output is enabled (SMR:SOE=1), da ta transmission is enabled (SCR:TXE=1) and data reception is disabled (SCR:RXE=0), and when the transmit data is written in the TDR, the SSR:TDRE bit is set to 0. This causes the first bit to output. Then, the transmit data is output in synchronization with a rising edge of the serial clock (SCK) output. 2. The SSR:TDRE bit is set to 1 before a half cycle of a falling edge of serial clock (SCK) output. Therefore, if the transmit interrupt is enabled (SCR:TIE=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. Data reception 1. If the serial data output is disabled (SMR:SOE=0), data transmission is enabled (SCR:TXE=1) and data reception is enabled (SCR:RXE=1), and when a dummy da ta is written in the TDR, the receive data is sampled at a falling edge of serial clock (SCK) output. 2. When the last bit is received, th e SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1) during this time, a r eceive interrupt request is output. The receive data (RDR) can be read during this time. 3. When the receive data (RDR) is read, the SSR:RDRF bit is cleared to 0. To perform data reception only, write a dummy data in the TDR so t hat the serial clock (SCK) is output. If the FIFO transmission and reception are enabled, th e serial clocks (SCK) for the preset number of frames are output when the transmit fra mes are set in the FBYTE register. Data transmission and reception 1. To perform data transmission and reception simultaneously, enable the serial data output (SMR:SOE=1) and enable the data transmission and reception (SCR:TXE, RXE=1). 2. When the transmit data is written in the TDR, the SSR:TDRE is set to 0 and the first bit is output. Then, the transmit data is output in synchronization with a rising edge of the serial clock (SCK) output. The SSR:TDRE bit is set to 1 before a half cycle of a falling edge of the first serial clock. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. 3. The receive data is sampled at a falling edge of th e serial clock (SCK) output. When the last bit of receive data is received, the SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive da ta (RDR) can be read during this time. When the receive data is read, the SSR:R DRF bit is cleared to 0. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 874 MB9Axxx/MB9Bxxx Series