Fujitsu Series 3 Manual

							 
5. Registers 
 
5. Registers 
This section explains the configuration and functions of the registers used for the \
10-bit A/D 
converter. 
 List of registers for  the 10-bit A/D converter 
Abbreviation Register  name See 
ADCR A/D Control Register  5.1 
ADSR A/D Status Register  5.2 
SCCR Scan Conversion Control Register  5.3 
SFNS Scan Conversion FIFO Stage Count Setup Register  5.4 
SCFD Scan Conversion FIFO Data Register  5.5 
SCIS Scan Conversion Input Selection Register  5.6 
PCCR Priority Conversion Control Register  5.7 
PFNS Priority Conversion FIFO  Stage Count Setup Register  5.8 
PCFD Priority Conversion FIFO Data Register  5.9 
PCIS Priority Conversion Input Selection Register  5.10 
CMPD A/D Comparison Value Setup Register  5.11 
CMPCR A/D Comparison Control Register  5.12 
ADSS Sampling Time Selection Register  5.13 
ADST Sampling Time Setup Register  5.14 
ADCT Comparison Time Setup Register  5.15 
 
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5. Registers 
 
5.1.  A/D Control Register (ADCR) 
The A/D Control Register (ADCR) performs interrupt flag display and interrupt enable control. 
 bit 15 14 13 12 11 10 9 8 
Field SCIF PCIF CMPIFRes ervedSCIE PCIE CMPIE OVRIE
Attribute R/W R/W R/W  - R/W R/W  R/W R/W 
Initial value 0 0 0  X 0 0  0 0 
 
[bit 15] SCIF: Scan conversion interrupt request bit  When conversion values are written up to the stage count specified in the Scan Conversion FIFO Stage 
Count Setup Register (SFNS) , this bit is set to 1. The read value of Read-Modify-Write access is 1 
regardless of the bit value. 
Description Bit  Read Write 
0 Conversion result is not stored.  Clears this bit. 
1 Conversion result is stored.  No effect. 
 
[bit 14] PCIF: Priority conversion interrupt request bit  When conversion values are written up to the stage speci fied in the Priority Conversion FIFO Stage Count 
Setup Register (PFNS), this bit is set to 1. The  read value of Read-Modify-Write access is 1 regardless 
of the bit value. 
Description Bit  Read Write 
0 Conversion result is not stored.  Clears this bit. 
1 Conversion result is stored.  No effect. 
 
[bit 13] CMPIF: Conversion result  comparison interrupt request bit 
When the condition set in the A/D Comparison Value Setup Register (CMPD) or A/D Comparison Control 
Register (CMPCR) is satisfied during the operation of  the A/D conversion result comparison function, this 
bit is set to 1. The read value of Read-Modify -Write access is 1 regardless of the bit value. 
Description Bit 
Read Write 
0 Specified condition is not satisfied.  Clears this bit. 
1 Specified condition is satisfied.  No effect. 
 
[bit 12] Reserved: Reserved bit  Write Has no effect on operation. 
Read The value is undefined. 
 
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5. Registers 
 
[bit 11] SCIE: Scan conversion interrupt enable bit This bit controls the interrupt request of SCIF. When the SCIE bit is enabled, and the SCIF bit is set, an 
interrupt request to the CPU is generated. 
Bit Description 
0 Interrupt request disable 
1 Interrupt request enable 
 
[bit 10] PCIE: Priority conversion interrupt enable bit  This bit controls the interrupt request of PCIF. When the PCIE bit is enabled, and the PCIF bit is set, an 
interrupt request to the CPU is generated. 
Bit Description 
0 Interrupt request disable 
1 Interrupt request enable 
 
[bit 9] CMPIE: Conversion resu lt comparison interrupt enable bit 
This bit controls the interrupt request of CMPIF. When  the CMPIE bit is enabled, and the CMPIF bit is set, 
an interrupt request to the CPU is generated. 
Bit Description 
0 Interrupt request disable 
1 Interrupt request enable 
 
[bit 8] OVRIE: FIFO overrun interrupt enable bit  This bit controls the interrupt request of the SOVR bit in the SCCR register or the POVR bit in the PCCR 
register. When the OVRIE bit is enabled, and the SOVR  or POVR bit is set, an interrupt request to the CPU 
is generated. 
Bit Description 
0 Interrupt request disable 
1 Interrupt request enable 
 
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5. Registers 
 
5.2.  A/D Status Register (ADSR) 
The A/D Status Register (ADSR) displays scan and priority conversion statuses. 
 bit 7 6 5 4 3 2 1 0 
Field ADSTPFDAS Reserved PCNS PCS SCS 
Attribute R/W  R/W - - - R  R R 
Initial value  0 0  X X X  0 0 0 
 
[bit 7] ADSTP: A/D conversion forced stop bit  Setting the ADSTP bit to 1 stops the A/D conversion operation forcibly (both scan and priority conversion 
operations are stopped). Forced stop of A/D conversion initializes the PCNS, PCS, and SCS bits in the 
ADSR register to 0. However, other register bits are not reset. 
Description Bit  Read Write 
0 No  effect. 
1 The value is always 0. 
Stops the conversion operation forcibly. 
 
[bit 6] FDAS: FIFO data placement selection bit  Setting the FDAS bit to 1 shifts the Scan Conver sion FIFO Data Register (SCFD) and Priority 
Conversion FIFO Data Register (PCFD) values by 6 b its to the LSB side, placing the conversion result in 
bit 9 to 0. 
When the FDAS bit is set to 1, the FIFO Data Registers (SCFD and PCFD) have no information about the 
converted channels. For this reason, use this bit when  channel information is not required (for example, 
conversion of only one channel is performed). 
When the FDAS bit is set to 1, the information of  the RS bit in the Priority Conversion FIFO Data 
Register (PCFD) is also lost. Use this  bit only for priority level 1 or 2. 
Bit Description 
0 Places conversion result on the MSB  side (with channel information). 
1 Places conversion result on the LSB side (without channel information). 
 
[bit 5:3] Reserved: Reserved bits  Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 2] PCNS: Priority conversion pending flag  This flag indicates that conversion at priority level 2 (software/timer) is pending. This flag is set when 
priority conversion at priority level 2 (software/timer) is started while priority conversion at priority level 1 
(external trigger start) is performed or when conver sion at priority level 1 is started while priority 
conversion at priority level 2 is performed. Writing is ignored. 
Bit Description 
0  Priority level 2 conversion is not pending. 
1  Priority level 2 conversion is pending. 
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5. Registers 
 
[bit 1] PCS: Priority conversion status flag This flag indicates that priority A/D conversion is in  progress. This flag is set while priority conversion at 
priority level 1 or 2 is performed. Writing is ignored. 
Bit Description 
0  Priority conversion is stopped. 
1 Priority conversion is in progress. 
 
[bit 0] SCS: Scan conversion status flag  This flag indicates that scan A/D conversion is in progress. Writing is ignored. 
Bit Description 
0  Scan conversion is stopped. 
1 Scan conversion is in progress. 
 
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CHAPTER  18-2: 10-bit  A/D Converter 
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5. Registers 
 
5.3.  Scan Conversion Control Register (SCCR) 
The Scan Conversion Control Register (SCCR) controls the scan conversion mode. 
 bit 15 14 13 12 11 10 9 8 
Field SEMP SFUL SOVR SFCLRReservedRPT SHEN SSTR 
Attribute  R R R/W  R/W - R/W  R/W R/W 
Initial value  1 0 0  0 X  0 0 0 
 
[bit 15] SEMP: Scan conversion FIFO empty bit  This bit is set when FIFO goes to the empty state. Wh en conversion data is written in the Scan Conversion 
FIFO Data Register (SCFD), this b it is set to 0. Writing is ignored. 
Bit Description 
0 Data remains in FIFO. 
1 FIFO is empty. 
 
[bit 14] SFUL: Scan conversion FIFO full bit  This bit is set when FIFO goes to full state. When SFC LR is set to 1 or the Scan Conversion FIFO Data 
Register (SCFD) is read, this bit is set to 0. Writing is ignored. 
Bit Description 
0  Data can be input to FIFO. 
1 FIFO is full. 
 
[bit 13] SOVR: Scan conversion overrun flag  This bit is set when an attempt to write data to a fu ll FIFO is made (conversion data in a full FIFO is not 
overwritten). The read value of Read-Modify-Write acces s is 1 regardless of the bit value. When the 
OVRIE bit in the ADCR register is 1, an interrupt is generated to the CPU if the SOVR bit is 1. 
Description Bit  Read Write 
0 No overrun has occurred.  Clears this bit. 
1 Overrun has occurred.  No effect. 
 
[bit 12] SFCLR: Scan conversion FIFO clear bit  Setting this bit to 1 clears the scan conversion FIFO. FIFO becomes empty and the SEMP bit is set to 1. 
Description Bit  Read Write 
0 No  effect. 
1 The value is always 0. 
Clears FIFO. 
 
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5. Registers 
 
[bit 11] Reserved: Reserved bit Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 10] RPT: Scan conversion repeat bit  Setting this bit to 1 places the converter in the rep eat mode. When the conversion of all analog input 
channels selected in the Scan Conv ersion Input Selection Register (SCI S) is completed, the conversion is 
started again. 
Setting the RPT bit to 0 ends the repeat conversion . The operation stops when the conversion of the 
analog input channels selected in the SCIS bit is completed. 
Setting the RPT bit to 1 must be performed while scan conversion is stopped (the SCS bit in the ADSR 
register = 0). (Setting the SSTR bit to 1 may be  performed simultaneously with setting the RPT bit to 
1.) 
Bit Description 
0  Single conversion mode 
1 Repeat conversion mode 
 
[bit 9] SHEN: Scan conversion timer start enable bit  Set this bit to 1 to start scan conversion using a risi ng edge from a timer. Software startup (SSTR = 1) is 
valid even when this bit is set to 1. 
Bit Description 
0  Timer start disable 
1 Timer start enable 
 
[bit 8] SSTR: Scan conversion start bit  Setting this bit to 1 starts A/D conversion. Setting this bit to 1 again during conversion stops the 
ongoing conversion immediately and restarts the conversion. 
Description Bit  Read Write 
0 No  effect. 
1 The value is always 0. 
Starts conversion or restarts the 
conversion (during conversion). 
 
 
If a startup  b

y a timer occurs simultaneously with the setting of th e 
 SSTR bit to 1, the setting of the SSTR 
bit to 1 takes preference and th e startup by the timer is ignored. 
 
 
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CHAPTER  18-2: 10-bit  A/D Converter 
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5. Registers 
 
5.4.  Scan Conversion FIFO Stage Count Setup Register (SFNS) 
The Scan Conversion FIFO Stage Count Setup Register (SFNS) sets up the generation of 
interrupt requests in scan conversion. When the specified count of FIFO stages store A/D 
conversion data, the interrupt request bit (SCIF) is set. 
 
bit 7 6 5 4 3 2 1 0 
Field Reserved SFS [3:0] 
Attribute  - - -  - R/W  R/W  R/W R/W 
Initial value  X X X  X 0 0  0 0 
 
[bit 7:4] Reserved: Reserved bits 
Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 3:0] SFS [3:0]: Scan conversion FIFO stage count setting bit  When A/D conversion data for the FIFO stage count (N  + 1) set in SFS [3:0] is written, the interrupt request 
flag (SCIF) is set to 1. 
Bit [3:0]  Description 
0b0000 Generates an interrupt request when convers
ion result is stored in the first FIFO 
stage. 
0b0001  Generates an interrupt request when conve
rsion result is stored in the second 
FIFO stage. 
0b0010  Generates an interrupt request when convers
ion result is stored in the third FIFO 
stage. 
... ... 
0b1101  Generates an interrupt request when conve
rsion result is stored in the 14th FIFO 
stage. 
0b1110  Generates an interrupt request when conve
rsion result is stored in the 15th FIFO 
stage. 
0b1111  Generates an interrupt request when conve
rsion result is stored in the 16th FIFO 
stage. 
 
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CHAPTER  18-2: 10-bit  A/D Converter 
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5. Registers 
 
5.5.  Scan Conversion FIFO Data Register (SCFD) 
The Scan Conversion FIFO Data Register (SCFD) consists of 16 FIFO stages and stores 
analog conversion results. Data can be retrieved sequentially by reading the register. 
 bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field SD9 SD8 SD7  SD6 SD5 SD4SD3SD2SD1SD0Res ervedSC4 SC3 SC2 SC1SC0
Attribute R R R R R  RRRR R R RR R R R
Initial value  X X X X X  XXXX X X X X  X X X
 
[bit 15:6] SD9:SD0:  Scan conversion result 
The result of 10-bit scan A/D conversion is written. 
[bit 5] Reserved: Reserved bit  The read value is 0. 
[bit 4:0] SC4:SC0: Conversion input channel bits  The analog input channels corresponding to the conversion result written in SD9 to SD0 are written. 
Settings for channels not defined in the product speci fications are not written. See the specified number of 
the analog input channels in th e Data Sheet of each product. 
Bit [4:0]  Description 
0b00000 ch.0 
0b00001 ch.1 
0b00010 ch.2 
... ... 
0b11101 ch.29 
0b11110 ch.30 
0b11111 ch.31 
 
 
This  reg

ister has different bit configurations depending on the FDAS bit setting in the A/D Status Register 
(ADSR). When the FDAS b it is 1

, see 3.2.6 Bit placement selection for FIFO data registers . 
To perform a byte access to t h

is register, read the mo st significant byte (bit 15:8) to shift the FIFO data. 
Reading the least significant byte (bit 7:0) does not shift FIFO. 
 
 
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CHAPTER  18-2: 10-bit  A/D Converter 
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5. Registers 
 
5.6.  Scan Conversion Input Selection Register (SCIS) 
The Scan Conversion Input Selection Register (SCIS) is used to select analog input channels 
for which scan conversion is performed. Any channels can be selected from multiple analog 
inputs. The selected channels are converted in ascending order of channel number. 
 SCIS3 (most significant byte: AN31 to  AN24) and SCIS2 (least significant 
byte: AN23 to AN16) 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field AN31 AN30 AN29 AN28 AN27 AN26AN25AN24AN23AN22AN21AN20 AN19 AN18 AN17AN16
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
  [bit 15:0] AN31:AN16: Analog input selection bits  When these bits are set to 1,  the corresponding channels are  selected for analog conversion. 
 SCIS1 (most significant byte: AN15 to  AN8) and SCIS0 (least significant byte: 
AN7 to AN0) 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field AN15 AN14 AN13 AN12 AN11 AN10AN9AN8AN7AN6AN5AN4AN3 AN2 AN1AN0
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
  [bit 15:0] AN15:AN0: Analog input selection bits  When these bits are set to 1,  the corresponding channels are  selected for analog conversion. 
 
It is not  p

ossible to change the channels during A/D conversion. Be sure to set SCIS3 to SCIS0 while the 
A/D conversi o

n is stopped. 
It is not possible to set 1 in the bit corresponding to a channel that is not defined in the product 
specifications. See the specified numbe r of the analog input channels in the Data Sheet of each product. 
 
 Example of scan conversion order 
The selected channels are converted in ascending order of channel number. 
Example:  When  the AN1, AN3, AN5,  and AN23  bits  are set to 1, the analog conversion proceeds 
from ch.1, ch.3, ch.5, and to ch.23. 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-2: 10-bit  A/D Converter 
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