Fujitsu Series 3 Manual

							 
5. USB host registers 
 
[bit 9] CANCEL (token CANCEL enable) 
This is s token cancellation enable bit. 
When 1 is set to this bit, if the target token is written to the Host Token Endpoint Register (HTOKEN) in 
the EOF area (specified in the EOF Se tting Register), its sending is canceled. When 0 is set to this bit, 
token sending is not canceled even if the target toke n is written to the register. The cancellation of token 
sending is detected by reading the TCAN bit of the Host Interrupt Register (HIRQ). 
Bit Description 
0  Continues a token. 
1 Cancels a token. 
 
 
This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
 
[bit 8] RETRY (RETRY enable) 
this is a retry enable bit. 
If this bit is set to 1, the target token is retried if a NAK or error* occurs. Retry processing is performed 
during the time that is specified in the Retry Timer Setting Register (HRTIMER). * :  HERR.RERR=1, HERR.TOUT=1, HERR. CRC=1, HERR.TGERR=1, HERR.STUFF=1 
Bit Description 
0 Does not retry token sending. 
1  Retries token sending. 
 
 
This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
 
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5. USB host registers 
 
[bit 7] RWKIRE (Remove WaKe up Interrupt Request Enable) 
This is a resume interrupt enable bit. 
When 1 is set to this bit, an interrupt occurs if the RWKIRQ bit of the Host Interrupt Register (HIRQ) is 
set to 1. When 0 is set to this bit, an interr upt does not occur even if the RWIRQ bit of the Host 
Interrupt Register (HIRQ) is set to 1. 
Bit Description 
0  Disables an interrupt after restarting. 
1  Enables an interrupt after restarting. 
 
 
This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
 
[bit 6] URIRE (Usb bus Rest Interrupt Request Enable) 
This is a bus reset interrupt enable bit. 
When 1 is set to this bit, an interrupt occurs if th e URIRQ bit of the Host Interrupt Register (HIRQ) is set 
to 1. When 0 is set to this bit, an interrupt does not occur even if the URIRQ bit of the Host Interrupt 
Register (HIRQ) is set to 1. 
Bit Description 
0  Disables an interrupt after resetting the USB bus. 
1  Enables an interrupt after resetting the USB bus. 
 
 
This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
 
[bit 5] CMPIRE (CoMPletion Interrupt Request Enable) 
This is a token completion interrupt enable bit. 
When 1 is set to this bit, an interrupt occurs if th e CMPIRQ bit of the Host Interrupt Register (HIRQ) is 
set to 1. When 0 is set to this bit, an interr upt does not occur even if the CMPIRQ bit of the Host 
Interrupt Register (HIRQ) is set to 1. 
Bit Description 
0  Disables an interrupt at completion. 
1  Enables an interrupt at completion. 
 
 
This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
 
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5. USB host registers 
 
[bit 4] CNNIRE (CoNNection Interrupt Request Enable) 
This is a device connection detection interrupt enable bit. 
When 1 is set to this bit, an interrupt occurs if the CNNIRQ bit of the Host Interrupt Register (HIRQ) is 
set to 1. When 0 is set to this bit, an interr upt does not occur even if the CNNIRQ bit of the Host 
Interrupt Register (HIRQ) is set to 1. 
Bit Description 
0  Disables an interrupt at device connection. 
1 Enables an interrupt at device connection. 
 
 
This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
 
[bit 3] DIRE (Disconnectio n Interrupt Request Enable) 
This is a device disconnection detection interrupt enable bit. 
When 1 is set to this bit, an interrupt occurs if the DIRQ bit of the Host Interrupt Register (HIRQ) is set to 
1. When 0 is set to this bit, an interrupt does  not occur even if the DIRQ bit of the Host Interrupt 
Register (HIRQ) is set to 1. 
Bit Description 
0  Disables an interrupt at device disconnection. 
1 Enables an interrupt at device disconnection. 
 
 
This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
 
[bit 2] SOFIRE (Start Of Frame Interrupt Request Enable) 
This is a SOF interrupt enable bit. 
When 1 is set to this bit, an interrupt occurs if th e SOFIRQ bit of the Host Interrupt Register (HIRQ) is 
set to 1. When 0 is set to this bit, an interr upt does not occur even if the SOFIRQ bit of the Host 
Interrupt Register (HIRQ) is set to 1. 
Bit Description 
0  Disables an interrupt when sending SOF. 
1  Enables an interrupt when sending SOF. 
 
 
This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
 
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5. USB host registers 
 
[bit 1] URST (Usb bus ReSeT) 
This is a bus reset bit. 
When 1 is set to this bit, the USB bus is reset. This bit continues set to 1 during USB bus resetting, and 
changes to 0 when USB bus resetting is ended. If 0  is set to this bit, no processing is performed. 
Bit Description 
0 Holds the status of the USB bus. 
1 Resets the USB bus. 
 
 

 No processing is performed even if this bit is set to 1 while the RST bit of the UDC Control Register 
(UDCC) is 1. 

 This bit cannot be set to 1 while the SUSP bit of the Host Status Register (HSTATE) is 1 or during 
token sending. 

 The Host Control Register (HCNT0 or HCNT1)  cannot be written while this bit is 1. 
 
[bit 0] HOST (HOST mode) 
This is a host mode bit. 
When 1 is set to this bit, the USB acts as a host. Wh en 0 is set to this bit, the USB acts as a function. 
Bit Description 
0 Function mode 
1 Host mode 
 
 

 This bit is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 

 Change the value of this bit while the RST bit  of the UDC Control Register (UDCC) is 1. 

 The operation mode does not transition to the require d one immediately after it was changed using this 
bit. Read this bit to check that the operation mode has changed. 

 Before changing from the host mode to the function mode, check that the following conditions are 
satisfied and also set 1 to the RST b it of the UDC Control Register (UDCC). 

 The SOFBUSY bit of the Host Status  Register (HSTATE) is set to 0. 

 The TKNEN bit of the Host Token Endpoint Register (HTOKEN) is set to 000. 

 The SUSP bit of the Host Status Register (HSTATE) is set to 0. 

 Before changing from the function mode to the host mode, set 1 to the HCONX bit of the UDC Control 
Register (UDCC), and disconnect the host or hub. 
 
 
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5. USB host registers 
 
5.2.  Host Interrupt Register (HIRQ) 
The Host Interrupt Register (HIRQ) indicates the USB host interrupt request flag. A host 
interrupt can occur by setting the interrupt enable bit of the Host Cont\
rol Register (HCNT0 or 
HCNT1), excluding the TCAN bit. 
 bit 7 6 5 4 3 2 1 0 
Field TCAN Reserved RWKIRQUR IRQCMPIRQCNNIRQ DIRQ SOFIRQ
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
Reset enabled    or not*  x x 
                  
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
 
[bit 7] TCAN (Token CANcel flag) 
This is a token cancellation flag. 
If this bit is set to 1, it means that token sending  is canceled based on the setting of the CANCEL bit of 
Host Control Register 1 (HCNT1). When this bit is 0 , it means that token sending is not canceled. If this 
bit is written with 0, it is set to 0. However, if  this bit is written with 1, its value is ignored. 
Bit Description 
0 Does not cancel token sending. 
1 Cancels token sending. 
 
 

 This bit is set to the initial value when 1 is set to the RST bit of the UDC Control Register (UDCC). 

 No interrupt occurs even if this bit is set. To carry  out interrupt processing, check that token sending is 
canceled during SOF in terrupt processing. 
 
[bit 6] Reserved bit 
This is a reserved bit. Always set it to 0. 
 
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[bit 5] RWKIRQ (Remove WaKe up Interrupt ReQuest) 
This is a remote Wake-up end flag. 
If this bit is set to 1, it means that remote Wake-up is ended. When this bit is 0, it has no meaning. If this 
bit is written with 0, it is set to 0. However, if this bit is written with 1, its value is ignored. 
When the RWKIRE bit of Host Control Register 0 (HCNT0) is 1, an interrupt occurs if this bit is set to 
1. 
Bit Description 
0  Issues no interrupt request by restart. 
1 Issues an interrupt request by restart. 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
[bit 4] URIRQ (Usb bus Reset Interrupt ReQuest) 
This is a bus reset end flag. 
If this bit is set to 1, it means that USB bus resetting  is ended. When this bit is 0, it has no meaning. If 
this bit is written with 0, it is set to 0. However,  if this bit is written with 1, its value is ignored. 
When the URIRE bit of Host Control Register 0 (HCNT0) is  1, an interrupt occurs if this bit is set to 1. 
Bit Description 
0 Issues no interrupt request by USB bus resetting. 
1 Issues an interrupt request by USB bus resetting. 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
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5. USB host registers 
 
[bit 3] CMPIRQ (CoMPletion Interrupt ReQuest) 
This is a token completion flag. 
If this bit is set to 1, it means that a token is completed. When this bit is 0, it has no meaning. If this bit 
is written with 0, it is set to 0. However, if  this bit is written with 1, its value is ignored. 
When the CMPIRE bit of Host Control Register 0 (HCNT0)  is 1, an interrupt occurs if this bit is set to 
1. 
Bit Description 
0  Issues no interrupt request by token completion. 
1 Issues an interrupt request by token completion. 
 
 

 This bit is set to the initial value when 1 is set to the RST bit of the UDC Control Register (UDCC). 

 This bit is not set to 1 even if the TCAN bit of  the Host Interrupt Register (HIRQ) changes to 1. 
 
[bit 2] CNNIRQ (CoNNection Interrupt ReQuest) 
This is a device connection detection flag. 
If this bit is set to 1, it means that a device connection is detected. When this bit is 0, it has no meaning. 
If this bit is written with 0, it is set to 0. However,  if this bit is written with 1, its value is ignored. 
When the CNNIRE bit of Host Control Register 0 (HCNT0) is 1, an interrupt occurs if this bit is set to 
1. 
Bit Description 
0  Issues no interrupt request by detecting a device connection. 
1 Issues an interrupt request by detecting a device connection. 
 
 

 This bit is set to the initial value when 1 is set to the RST bit of the UDC Control Register (UDCC). 

 A device connection is also de tected in the function mode. 
 
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5. USB host registers 
 
[bit 1] DIRQ (Disconnection Interrupt ReQuest) 
This is a device disconnection detection flag. 
If this bit is set to 1, it means that a device disconnection is detected. When this bit is 0, it has no 
meaning. If this bit is written with 0, it is set to 0. However, if this bit is written with 1, its value is 
ignored. 
When the DIRE bit of Host Control Register 0 (HCNT0) is  1, an interrupt occurs if this bit is set to 1. 
Bit Description 
0 Issues no interrupt request by detecting a device disconnection. 
1 Issues an interrupt request by detecting a device disconnection. 
 
 

 This bit is set to the initial value when 1 is set to the RST bit of the UDC Control Register (UDCC). 

 A device disconnection is also detected in the function mode. 
 
[bit 0] SOFIRQ (Start Of Frame Interrupt ReQuest) 
This is a SOF starting flag. 
If this bit is set to 1, it means that SOF token sending is  started. When this bit is 0, it has no meaning. If 
this bit is written with 0, it is set to 0. However,  if this bit is written with 1, its value is ignored. 
When the SOFIRE bit of Host Control Register 0 (HCNT0) is  1, an interrupt occurs if this bit is set to 1. 
Bit Description 
0 Does not issue an interrupt request by starting a SOF token. 
1 Issues an interrupt request by starting a SOF token. 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
 
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5. USB host registers 
 
5.3.  Host Error Status Register (HERR) 
The Host Error Status Register (HERR) indicates whether or not an error occurs while 
sending or receiving data in the host mode. 
 bit 15 14 13 12 11 10 9 8 
Field LSTSOFRERR TOUT CRC TGERRSTUFFHS 
Attribute  R/W R/W R/W  R/W R/W R/W  R/W 
Initial value 0 0 0  0 0 0  11 
Reset enabled or  not*   
                   
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
 
[bit 15] LSTSOF (LoST SOF) 
This is a lost SOF flag. 
If this bit is set to 1, it means that the SOF token cannot be sent in the host mode because other token is in 
process. When this bit is 0, it means that no lost SOF error is detected. If this bit is written with 0, it is 
set to 0. However, if this bit is written with 1, its value is ignored. 
Bit Description 
0 Sends SOF. 
1 SOF sending error 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
[bit 14] RERR (Receive Error) 
This is a receive error flag. 
When this bit is set to 1, it means that the received data exceeds  the specified maximum number of 
packets in the host mode. If a receive  error is detected, bit 5 (Timeout) of this register is also set to 1. 
When this bit is 0, it means that no error occurs. If this bit is written with 0, it is  set to 0. However, if 
this bit is written with 1, its value is ignored. 
Bit Description 
0  No receive error 
1 Maximum packet receive error 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
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[bit 13] TOUT (Time OUT) 
This is a timeout flag. 
If this bit is set to 1, it means that no response is returned from the device within the specified time after a 
token has been sent in the host mode. When this bit is 0, it means that no timeout is detected. When this 
bit is 0, it means that no error occurs. If this bit is written with 0, it is set to 0. However, if this bit is 
written with 1, its value is ignored. 
Bit Description 
0 No timeout 
1 Timeout occurs. 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
[bit 12] CRC (CRC error) 
This is a CRC error flag. 
If this bit is set to 1, it means that a CRC error is detected in the host mode. When this bit is 0, it means 
that no CRC error is detected. If a CRC error is detected, bit 5 (Timeout) of this register is also set to 1. 
When this bit is 0, it means that no CRC error is detect ed. If this bit is written with 0, it is set to 0. 
However, if this bit is written with 1, its value is ignored. 
Bit Description 
0  No CRC error 
1 CRC error occurs. 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
[bit 11] TGERR (ToGgle ERRor) 
This is a toggle error flag. 
If this bit is set to 1, it means that the data of this bit does not match the value of the received toggle data. 
When this bit is 0, it means that no toggle error is detected. If this bit is written with 0, it is set to 0. 
However, if this bit is written with 1, its value is ignored. 
Bit Description 
0  No toggle error. 
1 Toggle error occurs. 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
 
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