Fujitsu Series 3 Manual

							 
5. Registers 
 
5.3.  Low-voltage Detection Interrupt Clear Register (LVD_CLR) 
The Low-voltage Detection Interrupt Clear Register (LVD_CLR) clears a low-voltage detection 
interrupt cause. 
 
Bit 7 6 5 4 3 2 1 0 
Field LVDCLReserved 
Attribute  R/W - -  - - -  - - 
Initial value 1 0 0  0 0 0 0 0 
 
[bit 7] LVDCL: Low-voltage detection interrupt clear bit 
Bit Description 
0  Clears the low-voltage detection interrupt bit of the Low-voltage Detection 
Interrupt Register (LVD_STR) to 0. 
1 
Has no effect in write mode. [Initial value] 
 
1 is always set in read mode. 
 
[bit 6:0] Reserved: Reserved bits  0 is always set in read mode. 
This bit has no effect in write mode. 
 
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5. Registers 
 
5.4.  Low-voltage Detection Voltage Protection Register (LVD_RLR)  
The Low-voltage Detection Voltage Protection Register (LVD_RLR) write-protects the 
Low-voltage Detection Voltage Control Register (LVD_CTL). 
 
Bit 31 30 29 28 27 2625242322212019 18 1716
Field LVDLCK[31:16] 
Attribute R/W 
Initial  value  0x0000 
 
Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field LVDLCK[15:0] 
Attribute R/W 
Initial  value  0x0001 
 
[bit 31:0] LVDLCK[31:0]: Low-voltage Detect ion Voltage Control Register protection bit 
   Setting 0x1ACCE553 enables writing the Low-voltage  Detection Voltage Control Register (releases 
write protection mode). 
   Setting a value other than 0x1ACCE553 disables writing the Low-voltage Detection Voltage Control 
Register (enables write protection mode). 
   When the Low-voltage Detection Voltage Control Register is not set in write protection mode, 
0x00000000 is read. 
   When the Low-voltage Detection Voltage Control Register is set in write protection mode, 0x00000001 
is read. 
 
 
   Th e Low-vo ltag
e

 Detection Voltage Control Register (LVD_CTL) is write-protected in the initial state. 
To write the  L

VD_CTL Register, set 0x1ACCE553 to the Low-voltage Detection Voltage Protection 
Register (LVD_RLR) to release write protection mode. 
   To enable write protection mode of the LVD_CTL register, set a value other than 0x1ACCE553 to the 
Low-voltage Detection Voltage Protection Register (LVD_RLR). 
   Once write protection mode is released for the LVD_ CTL Register, it remains released until a value other 
than 0x1ACCE553 is written to the LVD_RLR Register. 
 
 
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 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Low-voltage Detection 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  16  
5.5.  Low-voltage Detection Circuit Status Register 
(LVD_STR2) 
The Low-voltage Detection Circuit Status Register (LVD_STR2) checks the operation status of 
a low-voltage detection interrupt. 
 
bit 7 6 5 4 3 2 1 0 
Field LVDIRDY Reserved 
Attribute  R - -  - - -  - - 
Initial value 0 1 0  0 0 0 0 0 
 
[bit7] LVDIRDY : Low-voltage detection interrupt status flag 
bit Description 
0  Stabilization wait state or monitoring stop state [Initial value] 
1 Monitoring state 
 
This bit has no effect in write mode. 
 
[bit6:0] Reserved : Reserved bits  Read value has no meaning. 
This bit has no effect in write mode. 
 
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1. Overview of Low Power Consumption Mode 
 
Chapter: Low Power Consumption Mode 
This chapter describes the functions and operations of low power consumption mode. 
 
1.
 Overview of Low Power Consumption Mode 
2. Configuration of CPU Operation Modes 
3. Operations of Standby Modes 
4. Standby Mode Setting Procedure Examples 
5. List of Low Power Consumption Registers 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFLPMODE-E01.2 
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1. Overview of Low Power Consumption Mode 
 
1.  Overview of Low Power Consumption Mode 
To reduce the power consumption, the system provides low power consumption mode, which 
enables the use of three types of standby modes: SLEEP, TIMER, and STOP modes. 
 Overview of CPU operation modes 
CPU operation modes are classified into the following types. 
  RUN modes 
  High speed CR run mode 
   Main run mode 
   PLL run mode 
   Low speed CR run mode 
   Sub run mode 
 SLEEP modes 
  High speed CR sleep mode 
   Main sleep mode 
   PLL sleep mode 
   Low speed CR sleep mode 
   Sub sleep mode 
 TIMER modes 
  High speed CR timer mode 
   Main timer mode 
   PLL timer mode 
   Low speed CR timer mode 
   Sub timer mode 
 STOP mode 
 
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1. Overview of Low Power Consumption Mode 
 
 Overview of RUN mode 
RUN mode is defined with a clock selected as a mast er clock. The base clocks, which are obtained by 
dividing the master clock frequency, are supplied to CPU clock, AHB bus clock, and APB bus clock to run 
the CPU, buses, and most peripherals.   
The source clock frequency can be changed dynamically. When not using the main or sub oscillator, the 
source clock oscillator can be stopped. 
RUN mode is divided into the following modes depending on the clock selected as a master clock. 
  High speed CR run mode 
In this mode, the high speed CR oscillator clock is used as a master clock. When not using the main or sub 
oscillator, the respective oscillators can be stopped.  The low speed CR oscillator is always set to the active 
state. It changes to this mode  after a reset has been released. 
 Main run mode 
In this mode, the main oscillator clock is used as a master clock. The status of the PLL Multiplier Circuit or 
sub oscillator varies depending on the setting of the PLLE or SOSCE bit. The high and low speed CR 
oscillators are always set to the active state. 
  PLL run mode 
In this mode, the PLL clock obtained by multiplying the main oscillator clock is used as a master clock. The 
main, high speed CR, and low speed CR oscillators are al ways set to the active state. The status of the sub 
oscillator varies depending on the setting of the SOSCE bit. 
  Low speed CR run mode 
In this mode, the low speed CR oscillator clock is used as a master clock. The status of the sub oscillator 
varies depending on the setting of the SOSCE bit. The main oscillator, high speed CR oscillator, and PLL 
Multiplier Circuit are not available in this mode. 
  Sub run mode 
In this mode, the sub oscillator clock is used as a mast er clock. The low speed CR oscillator is always set to 
the active state. The main oscillator, high speed CR oscillator, and PLL Multiplier Circuit are not available 
in this mode. 
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1. Overview of Low Power Consumption Mode 
 
 Overview of SLEEP mode 
SLEEP mode is classified as one of standby modes. SLEEP mode is used to stop CPU clocks. This causes 
the CPU to be stopped, reducing the power consumption. The resources connected to the AHB and APB bus 
clocks continue operations. 
SLEEP mode is divided into the following modes depe nding on the clock selected as a master clock. 
 High speed CR sleep mode 
When the high speed CR oscillator clock is selected as a master clock, the system changes to high speed CR 
sleep mode if the transition to SLEEP mode is reques ted. In this mode, the status of the main or sub 
oscillator varies depending on the setting of the MOSCE or SOSCE bit. The low speed CR oscillator is 
always set to the active state. 
  Main sleep mode 
When the main clock is selected as a master clock, th e system changes to main sleep mode if the transition 
to SLEEP mode is requested. In this mode, the status of the PLL Multiplier Circuit or sub oscillator varies 
depending on the setting of the PLLE or SOSCE bit.  The high and low speed CR oscillators are always set 
to the active state. 
  PLL sleep mode 
When the PLL clock is selected as a master clock, the  system changes to PLL sleep mode if the transition to 
SLEEP mode is requested. In this mode, the main, hi gh speed CR, and low speed CR oscillators are always 
set to the active state. The status of the sub oscillator varies depending on the setting of the SOSCE bit. 
  Low speed CR sleep mode 
When the low speed CR clock is selected as a master  clock, the system changes to low speed CR sleep 
mode if the transition to SLEEP mode is requested. In  this mode, the status of the sub oscillator varies 
depending on the setting of the SOSCE bit. The main oscillator, high speed CR oscillator, and PLL 
Multiplier Circuit are not available in this mode. 
  Sub sleep mode 
When the sub clock is selected as a  master clock, the system changes to  sub sleep mode if the transition to 
SLEEP mode is requested. In this mode, the low speed  CR oscillator is always set to the active state. The 
main oscillator, high speed CR oscillator, and PLL Multiplier Circuit are not available in this mode. 
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1. Overview of Low Power Consumption Mode 
 
 Overview of TIMER mode 
TIMER mode is classified as one of standby modes. TIMER mode is used to stop supplying a base clock. 
This causes the CPU clock, AHB bus clock, and all APB bus clocks to be stopped, reducing the power 
consumption. In this case, all functions are stopped, excluding the oscillators, PLL, hardware watchdog 
timer, watch counter, clock failure detector, and Low Voltage Detection Circuit. 
TIMER mode is divided into the following modes depending on the clock selected as a master clock. 
  High speed CR timer mode 
When the high speed CR oscillator clock is selected as a master clock, the system changes to high speed CR 
timer mode if the transition to TIMER mode is reques ted. In this mode, the status of the main or sub 
oscillator varies depending on the setting of the MOSCE or SOSCE bit. The low speed CR oscillator is 
always set to the active state. 
  Main timer mode 
When the main clock is selected as a master clock, th e system changes to main timer mode if the transition 
to TIMER mode is requested. In this mode, the status  of the PLL Multiplier Circuit or sub oscillator varies 
depending on the setting of the PLLE or SOSCE bit.  The high and low speed CR oscillators are always set 
to the active state. 
  PLL timer mode 
When the PLL clock is selected as a master clock, the  system changes to PLL timer mode if the transition to 
TIMER mode is requested. In this mode, the main, hi gh speed CR, and low speed CR oscillators are always 
set to the active state. The status of the sub oscillator varies depending on the setting of the SOSCE bit. 
  Low speed CR timer mode 
When the low speed CR clock is selected as a master  clock, the system changes to low speed CR timer 
mode if the transition to TIMER mode is requested. In this mode, the status of the sub oscillator varies 
depending on the setting of the SOSCE bit. The main oscillator, high speed CR oscillator, and PLL 
Multiplier Circuit are not available in this mode. 
  Sub timer mode 
When the sub clock is selected as a  master clock, the system changes to sub timer mode if the transition to 
TIMER mode is requested. In this mode, the sub oscilla tor and low speed CR oscillator are always set to the 
active state. The main oscillator, high speed CR oscilla tor, and PLL Multiplier Circuit are not available in 
this mode. 
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1. Overview of Low Power Consumption Mode 
 
 Overview of STOP mode 
STOP mode is classified as one of standby modes. ST OP mode is used to stop all oscillating operations. 
Enabling this mode stops all functions, excluding the Lo w Voltage Detection Circuit. This therefore allows 
data to be held with the minimum power consumption. 
  Relationships between CPU operation modes and consumption current 
values. 
Figure 1-1  shows the relationships between CPU operation modes and consumption current values. 
Figure 1-1 Relationships between CPU operation modes and consumption current values 
PLL run mode
Main run mode
High speed CR 
run mode
Sub run mode
Low speed CR run mode
Consumption current
PLL sleep mode
Main sleep mode
High speed CR sleep mode
Sub sleep mode
Low speed CR sleep mode
PLL timer mode
Main timer mode
High speed CR  timer mode
Sub timer mode
Low speed CR timer mode
STOP mode
Standby mode
 
 
 
The figure  above s

hows only the approximate consumption current valu es. The act
 ual consumption current 
values vary depending on the oscillator and PLL starting conditions in each mode or the clock configuration 
of the selected frequency and other elements. 
 
 
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