Fujitsu Series 3 Manual

							 
1. Overview of USB host 
 
Chapter: USB Host 
This chapter explains the functions and operations of the USB host. 
 
1.
   Overview of USB host
2.
   USB host configuration
3.
   USB host operations
4.
   USB host setting procedure examples
5.
   USB host registers
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FW03H
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E18.2 
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1. Overview of USB host 
 
1.  Overview of USB host 
This section explains the functions and operations of the USB host. 
 Features of USB host 
The USB host has the following features: 
  Automatic detection of full-speed or low-speed transfer 
   Support of full-speed or low-speed transfer 
   Automatic detection of device connection or disconnection 
   Support of USB bus reset sending function 
   Support of IN, OUT, SETUP, and SOF tokens 
   Automatic sending of handshake packet for IN token (excluding STALL) 
   Automatic detection of handshake packet for OUT token 
   Support of maximum packet length of up to 256 bytes 
   Support of actions against errors ( CRC error, toggle error, and timeout) 
   Support of Wake-up function 
   Support of FUJITSUs original USB host functions Can also be operated as USB functions by switching 
the operation mode. (For restrictions in the USB host specifications, see  Ta b l e  1 - 1.) 
 
 
Set th

e base clock to 13 MHz or higher when using the USB host. 
 
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1. Overview of USB host 
 
Table 1-1 Restrictions in USB host specifications  Host 
o*1 
Hub support 
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Bulk transfer  o Transfer functions 
Control transfer  o 
Interrupt transfer o 
Isochronous t

ransfer  o 
Low Speed  o Transfer speed modes 
Full Speed o 
PRE packet support  x 
SOF packet support o 
CRC error o Error types 
Toggle error  o 
Timeout o 
Max. packet < Received data  o 
Detection of device connection or disconnection  o 
Detection of transfer speed  o 
o: Supported. 
x: Not supported. 
 
*1 : Supports a hub of up to one stage in only the full-speed mode. 
 
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2. USB host configuration 
 
2.  USB host configuration 
Figure 2-1 shows the USB host block diagram. 
 USB host block diagram 
Figure 2-1 USB host block diagram 
 
On-chip bus
UDP
UDM
UDC
CPU interface
UDCC
HCNT0,1 HIRQ
HERR
HSTATE
HFCOMP
HRTIMER HADRHEOF
HFRAME HTOKEN
UDC 
interface
USB clock (48 MHz)
From USB clock 
generation unit
I/O
Interrupt
Interrupt
SUSP
Endpoint 1  buffer
Endpoint 2 
buffer
Host 
control unit
  
 
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3. USB host operations 
 
3.  USB host operations 
This section explains the operations of the USB host. 
 
3.1 Device connection  
3.2  USB bus resetting  
3.3  Token packet  
3.4  Data packet  
3.5  Handshake packet  
3.6  Retry function  
3.7  SOF interrupt  
3.8  Error status  
3.9  End of packet  
3.10  Suspend and resume operations  
3.11  Device disconnection 
 
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3. USB host operations 
 
3.1. Device connection 
This section shows how to detect that an external USB device is connected using software. 
 Host function setting 
To carry out USB operation, configure the setting of the USB clock generation unit and enable the USB 
clock output while the USBEN bit of the USB Enable  Register (USBEN) is 0 (USB operation disabled). 
Next, set the USBEN bit to 1 (USB operation enabled).  Then, to operate the USB as a host, set 1 to the 
HOST bit of Host Control Register 0 (HCNT0). 
  When an external USB device is not connected or connected 
When an external USB device is not connected, both of host pins D+ and D- are set to LOW by the 
pull-down resistor. In this case, the CSTAT bit of  the Host Status Register (HSTATE) is 0 and the 
TMODE bit is undefined. When an external USB devi ce is connected, the CSTAT bit of the Host Status 
Register (HSTATE) is changed to 1. 
  Detection of external USB device connection 
When a connection of an external USB device is detect ed, the CNNIRQ bit of the Host Interrupt Register 
(HIRQ) is set to 1. If 1 is set to the CNNIRE  bit of Host Control Register 0 (HCNT0), a device 
connection interrupt occurs. To clear this interrupt,  write 0 to the CNNIRQ bit of the Host Interrupt 
Register (HIRQ). When detecting a device connection by polling, instead of an interrupt, use the following 
steps to create a program. 
1.  Set the CNNIRE bit of Host Control Register 0 (HCNT0) to 0. 
2.  Check that the CNNIRQ bit of the Host In terrupt Register (HIRQ) changes to 1. 
 Obtaining the transfer speed of the  remote USB device and selecting clocks 
To obtain the possible transfer speed of the remote US B device after detecting a connection, check the value 
of the TMODE bit of the Host Status Register (HSTATE). The following shows the relationships between 
the transfer speed and the value of the TMODE  bit of the Host Status Register (HSTATE). 
   The destination is a device in the full-speed mode. -> TMODE=1 
   The destination is a device in the low-speed mode. -> TMODE=0 
 
If the RST bit of the UDC control register (UDCC) is 1  after obtaining the transfer speed of an external 
USB device, update the CLKSEL bit of the Host Status Register (HSTATE) according to the obtained 
transfer speed. 
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3. USB host operations 
 
Figure 3-1 Full-speed device connection detection timing example (HCNT0 bit 0=0) 
 
FUJITSU SEMICONDUCTOR LIMITED 
 
Device 
connection
Host pin D
 + 
Host pin D - 
2.5  s or more
CSTAT bit of HSTATE
Undefined
TMO D
 E bi

t of HSTATE
CNNIRQ bit of HIRQ
 
 0 
 
HOST bit of HCNT
 
 
  When 2. 5

s laps ed
  after an external USB device was co nnected, the CSTAT bit of the Host Status 
Register (HSTATE) is changed to 1. 
   The TMODE and CSTAT bits of the Host Status Regi ster (HSTATE) are updated regardless of the setting 
of the HOST bit of Host Control Register 0 (HCNT0). The CNNIRQ and DIRQ bits of the Host Interrupt 
Register (HIRQ) are set to 1  if conditions are satisfied. 
 
 
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3. USB host operations 
 
3.2.  USB bus resetting 
The USB bus is reset by sending SE0 for 10 ms or more if the URST bit of Host Control 
Register 0 (HCNT0) is set to 1 in the host mode. After USB bus resetting has been 
completed, the URST bit of Host Control Register 0 (HCNT0) is set to 0, and the URIRQ bit 
of the Host Interrupt Register (HIRQ) is set to 1
. If the URIRE bit of Host Control Register 0 
(HCNT0) is then set to 1, an interrupt occurs. To clear this interrupt, write 0 to the URIRQ 
bit of the Host Interrupt Register (HIRQ). 
  Notes on before and after resetting the USB bus 
Note on the following points when resetting the USB bus. 
1.  To check that the device is connected before resetting the USB bus, make sure that the CSTAT bit of the 
Host Status Register (HSTATE) is set to 1. 
2.  Resetting the USB bus changes the CSTAT bit of the Host  Status Register (HSTATE) to 0, resulting in 
the USB device being disconnected. At this time, the  DIRQ bit of the Host Interrupt Register (HIRQ) is 
not set to 1. 
3.  After USB bus resetting has been completed, compare  the value of the CLKSEL bit with that of the 
TMODE bit in the Host Status Register (HSTATE). If they do not match, update the CLKSEL bit to 
make a match. Update the CLKSEL bit when the RST  bit of the UDC Control Register (UDCC) is 1. 
4.  After USB bus resetting has been completed, check that the USB device is connected using one of the 
bits shown below, and execute token processing. 
  CNNIRQ bit of Host Interrupt Register (HIRQ) 
   CSTAT bit of Host Status Register (HSTATE) 
 
Figure 3-2 Device resetting timing example 
 
FUJITSU SEMICONDUCTOR LIMITED 
 
10  ms or more
Host pin D +
Host pin D
 -
 0 URST bit of HCNT
CSTAT bit of HSTATE
URIRQ bit of HIRQ
 
CNNIRQ bit of HIRQ 
Write  1  to the  2.5 s or more 
URST bit of HCNT .
 
 
 
No to

ken is issued if a connection of the USB device is not detected after USB bus resetting has been 
completed.   
 
 
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3. USB host operations 
 
3.3. Token packet 
When issuing an IN, OUT, or SETUP token in the host mode, use the following setting steps to 
send a token packet. 
1.  Set the Host Address Register (HADR). 
2.  Set the DIR and PKS bits of the E
P1 Control Register (EP1C) or EP2 Control Register 
(EP2C). 
3.  Write the required data to the Host Token Endpoint Register (HTOKEN). 
When issuing an SOF token, set the Frame  Setup Register (HFRAME) and EOF Setup 
Register (HEOF), and write the required data to  the Host Token Endpoint Register (HTOKEN). 
The setting above is not required if no change is made in the HADR, EP1C, EP2C, HFRAME, 
and HEOF registers. 
  Token packet setting 
In the host mode, use endpoint 1 and end point 2 buffers to send and receive data. 
When issuing an IN, OUT, or SETUP token, specify  the target address in the Host Address Register 
(HADR). Then, specify the maximum  number of bytes for each packet in the PKS bit and the transfer 
direction of each packet in the DIR bit of the EP1 Control Register (EP1C) or EP2 Control Register (EP2C) 
respectively. 
If the DIR bit of the EP1 Control Register (EP1C) is 1 , the endpoint 1 buffer is used as an OUT buffer. 
The endpoint 2 buffer is used as an IN buffer. Then set 0 to the DIR bit of the EP2 Control Register 
(EP2C). 
If the DIR bit of the EP1 Control Register (EP1C) is 0,  the endpoint 1 buffer is used as an IN buffer. The 
endpoint 2 buffer is used as an OUT buffer. Then set 1 to the DIR bit of the EP2 Control Register (EP2C). 
Take the following steps to execute token processing. 
1.  Specify the DIR and PKS bits of the EP1 Control Register (EP1C) and EP2 Control Register (EP2C). 
2.  If the target endpoint n (n: 1 or 2) is set to the OUT direction, write send data to the endpoint n (n: 1 or 
2) buffer. Also set 0 to the DRQ bit of the EPn Status Register (EPnS: n = 1 or 2). 
If the IN direction is selected, read the DRQ bit of the EPn Status Register (EPnS: n = 1 or 2), and check 
that its value is 0. 
3.  Specify the target endpoint, token, and toggle data in the Host Token Endpoint Register (HTOKEN). 
 
The USB circuit sends a token packet in the order of Sync, token, address, endpoint, CRC5, and EOP based 
on the specified token; however, Sync, CRC5, and EOP  are sent automatically. After one packet has been 
sent, the CMPIRQ bit of the Host Interrupt Register (H IRQ) is set to 1. The TKNEN bit of the Host Token 
Endpoint Register (HTOKEN) is set to 0b000 (see  3.7 SOF interrupt ). At this time, if the CMPIRE bit 
of  Host C
ont

rol Register 0 (HCNT0) is 1, an interr upt occurs. To clear this interrupt, write 0 to the 
CMPIRQ bit of the Host In terrupt Register (HIRQ). 
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3. USB host operations 
 
Figure 3-3 Example of register setting to issue an IN, OUT, or SETUP token 
 
Write to HADR
(if a change is required)Write to EP1C or EP2C.
(if a change is required)
Write to HTOKEN.
Register write signal
Check the status of the endpoint 1 or 2 buffer.
  
 
When issuing an SOF token, specify the EOF time  in the EOF Setup Register (HEOF) and the frame 
number in the Frame Setup Register (HFRAME) respectively. Then specify an SOF token code in the 
TKNEN bit of the Host Token Endpoint Register (HTOKEN). After this, send Sync, SOF token, frame 
number, CRC5, and EOP are sent, the SOFBUSY bit of the Ho st Status Resister (HSTATE) is set to 1, and 
the Frame Setup Register (HFRAME)  is incremented by one. The CMPIRQ bit of the Host Interrupt 
Register (HIRQ) is also set to 1, causing the TKNEN bit of the Host Token Endpoint Register (HTOKEN) 
to be cleared to (000)b.  If the CMPIRE bit of Host Control Register  0 (HCNT0) is 1, an interrupt occurs. 
When SOF is sent automatically, an interrupt by CMPIRQ does not occur. To clear a token completion 
interrupt, write 0 to the CMPIRQ bit of  the Host Interrupt Register (HIRQ). 
SOF is automatically sent every 1 ms while the SOFBUSY  bit of the Host Status Register (HSTATE) is 1. 
The following shows the conditions (SOF stop conditi ons) to set the SOFBUSY bit of the Host Status 
Register (HSTATE) to 0. 
  Write 0 to the SOFBUSY bit of the Host Status Register (HSTATE). 
   Reset the USB bus (write 1 to the URST bit of HCNT). 
   Write 1 to the SUSP bit of the Host Status Register (HSTATE). 
   Disconnect the USB device (when the CSTAT bit of HSTATE is 0). 
 
Take the following steps to change the USB from the host mode to the function mode. 
1.  Set 0 to the SOFBUSY bit of the Host Status Register (HSTATE). 
2.  Check the following conditions. 
   The SOFBUSY bit of the Host Status Re gister (HSTATE) is cleared to 0. 
   The TKNEN bit of the Host Token Endpoint Register (HTOKEN) is set to 000. 
   The SUSP bit of the Host Status Register (HSTATE) is set to 0. 
3.  Set 1 to the RST bit of the UDC Control Register (UDCC). 
4.  Change the operation mode from the host mode to the function mode. 
 
To set the SOFBUSY bit of the Host Status Register (HSTATE) to 1 again, send an SOF token once more. 
The EOF Setup Register is used to prevent SOF from being sent simultaneously with other tokens. If the 
TKNEN bit of the Host Token Endpoint Register (HTO KEN) is written in the period from the EOF setting 
time to the SOF starting time, the specified token is pl aced into the wait state. After SOF has been sent, the 
token in the wait state is issued. The EOF Setup Register  specifies a 1-bit time as the time unit. For example, 
if (10)h is specified in the EOF Setup Register, th e time is set to 16*1/12MHz=1333.3ns in the full-speed 
mode and 16*1/1.5MHz=10666.6ns in the low-speed mode. When the EOF setting time is shorter than the 
1-packet time, SOF may be sent doubly during execution of other token. In this case, the LSTSOF bit of the 
Host Error Status Register (HERR) is set to 1, and  SOF is not sent. If 1 is set to the LSTSOF bit of the 
Host Error Status Register (HERR), the value of  the EOF Setting Register must be increased (see the 
explanation of the EOF Setup Register). 
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