Fujitsu Series 3 Manual

							 
7. Registers 
 
 
 If you write a disabled value to a WWEC, WADC or WA CC bit, operation of the external bus interface is 
not guaranteed. 

 In NAND flash memory mode, the MNWEX and MNREX timings are set by the timing registers as is 
the case with MWEX and MOEX. 
 
 
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7. Registers 
 
7.3.  Area Register 0 to Area Register 7 
The following shows the configuration of the Area Register (0 to 7). 
 
bit 31 30 29 28 27 2625242322212019 18 17 16
Field Reserved MASK 
Attribute -  R/W 
Initial 
value  - 001111 (16MB width) 
                   
bit  15 14  13 12  11 10 9 8 7 6 5 4 3 2 1 0 
Field Reserved  ADDR 
Attribute -  R/W 
Initial 
value  -  (from MCSX[0])
 
00000000, 00010000, 00100000,   
00110000, 01000000, 01010000,    01100000, 01110000 
*1 
 
[bit 22:16] MASK: address mask 
These bits set the value to mask the value set in ADDR. 
If 1 is set as a mask value, the  external bus interface masks each of  the internal bus and ADDR according 
to the value, and compares the masking results. If  the results are matched, the external bus interface 
accesses the MCSX signal. 
Example: 
ADDR = 0b00001000 
MASK = 0b 0000011 
 An example where a device is selected  Internal bus address (External interface address) AD = 0x10900000 
Masking 
ADDR & (!MASK)  =0b00001000 
AD [27:20] & (!MASK)  =0b00001000      ….. Matched. The device is selected 
 An example where a device is not selected Internal bus address (External interface address) AD = 0x10C00000 
Masking 
ADDR & (!MASK)  =0b00001000 
AD [27:20] & (!MASK)  =0b00001100      …..Not matched. The device is not selected 
An area size is selected for mask ing. In the example, 0x10800000 0x10B00000 (4 MB) is selected. 
A bit set to 1 for masking is lost during masking proces s. The bit is disabled even if it is set in ADDR. In 
the example, if LSB is set to 1 (ADDR=0b00001001), it is disabled during masking and the same address 
area is selected. The following example indicates the  relationship between the mask settings and the address 
area size. 
0b0000000   1MB  0b0000111   8MB 
0b0000001   2MB  0b0001111   16MB 
0b0000011   4MB  0b001 1111  32MB 
 
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Chapter: External Bus Interface 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  32 
[bit  7:0] ADDR: Address 
These bits specify the address to  set the corresponding MCSX area. 
The address is in the fixed 256 MB area assigned to the SRAM/flash memory interface. 
The address specified by bits 7:0 corresponds to the internal address [27:20]. 
 
No address areas must overlap other areas. 
If unused MCSX is accessed, operation of the exte rnal bus interface is also not guaranteed. 
 
 
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1. Overview 
 
Chapter: Debug Interface 
This chapter explains the function and operation of the debug interface. 
 
1.
 Overview 
2. Pin Description 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFDEBUG-E01.2 
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1. Overview 
 
1. Overview 
This series contains a Serial Wire JTAG Debug Port (SWJ-DP). 
Connecting an ICE to the SWJ-DP allows system debugging. 
This series also contains an Embed

ded Trace Macro Cell (ETM) for tracing instructions and a 
Trace Port Interface Unit (TPIU) that controls trace data. 
This section describes the functions of the pins to be used for debugging. 
For details on the SWJ-DP, ETM, TPIU and system  debug, see Cortex-M3 Technical Reference Manual. 
 Features 
Five pins are assigned to the SWJ-DP. 
These five pins are initially dedicated to the JTAG. It is possible to change their functions to the serial wire 
debug mode. 
It is possible to output inst ruction trace by selecting it from 4-bit trace data (TRACED0-3) and 
asynchronous trace data (SWO). 
 
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2. Pin Description 
 
2. Pin Description 
This section describes pins. 
 
2.1 Pins for Debug Purposes  
2.2  ETM Pins  
2.3  Functions Initially Assigned to Pins  
2.4  Internal Pull-Ups of JTAG Pins 
 
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2. Pin Description 
 
2.1.  Pins for Debug Purposes 
Five pins (TRSTX, TCK, TMS, TDI, and TDO) are assigned to the JTAG and two pins 
(SWCLK and SWDIO) are assigned to the serial wire. In addition, a Serial Wire Viewer signal 
(SWO) that outputs trace data is assigned. 
TMS is shared with SWDIO, TCK is shared with SWCLK, and TDO is shared with SWO. 
The following provides a list of pin functions in each debug mode. 
Table 2-1 SWJ-DP pin functions in debug mode Pin JTAG  Serial Wire/Trace 
TCK/SWCLK  TCK (JTAG Clock signal)  SWCLK (Serial Wire Clock signal) 
TMS/SWDIO TMS (JTAG State Mode signal)  SWDIO (Serial Wire Data Input/Output signal) 
TDI  TDI (JTAG Data Input signal)  - 
TDO/SWO TDO (JTAG Data Output signal)  SWO (Serial Wire Viewer Output signal) 
TRSTX TRSTX (active-LOW JTAG Reset signal) - 
 
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2. Pin Description 
 
2.2. ETM Pins 
The ETM is assigned four trace outputs (TRACED0, TRACED1, TRACED2, and TRACED3) 
and one clock (TRACECLK). 
The following provides a list of pin functions in each debug mode. 
Table 2-2 Trace pin functions in debug mode Pin Trace 
TRACED0 Synchronous  Trace Data Output signal 
TRACED1 Synchronous  Trace Data Output signal 
TRACED2 Synchronous  Trace Data Output signal 
TRACED3 Synchronous  Trace Data Output signal 
TRACECLK  Trace Clock signal 
 
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2. Pin Description 
 
2.3.  Functions Initially Assigned to Pins 
The 10 pins - five JTAG pins and five ETM trace pins - are used also as GPIO. 
Five JTAG pins (TRSTX, TCK, TMS, TDI, and TDO) are initially dedicated to debug function, 
whereas five ETM pins (TRACED0, TRACED1, TRACED2, TRACED3, and TRACECLK) are 
not initially dedicated to that. 
When using this series, please configure these ETM pins to provide the debug function. 
Note:  For details on how to set the debug function, see Chapter I/O Ports   
The following table provides initial states after resets  are cleared and the functions that can be changed by 
setting PFRs (Port function registers). 
Note:  For details on the PFRs, see Chapter I/O Ports. 
Table 2-3 Functions initially assigned to pins for debugging purposes and change of function 
   Initially assigned pin 
function  Change of function by setting 
the PFR 
TCK/SWCLK TCK  GPIO 
TMS/SWDIO TMS GPIO 
TDI TDI GPIO 
TDO/SWO TDO  GPIO 
JTAG pins 
TRSTX TRSTX GPIO 
TRACED0 GPIO  TRACED0 
TRACED1 GPIO TRACED1 
TRACED2 GPIO TRACED2 
TRACED3 GPIO TRACED3 
ETM pins 
TRACECLK GPIO TRACECLK 
 
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