Fujitsu Series 3 Manual

							 
1. Overview 
 
CHAPTER: Interrupts 
This chapter explains the interrupt controller and peripheral interrupt requests. 
 
1.
 Overview 
2. Structure 
3. Exception and Interrupt Vectors 
4. Registers 
5. Usage Warnings 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFIRQC-E01.2 
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1. Overview 
 
1. Overview 
The interrupt controller determines the priority of interrupt requests and sends the requests to 
the CPU. The Cortex-M3 CPU core is equipped with the nested vectored interrupt controller 
(NVIC) internally within the core. Interrupt signals from several peripherals are aggregated 
and input to a single interrupt vector. The interrupt requests that have occurred can be 
checked using the interrupt request batch read register. Furthermore, for some of the interrupt 
sources, the interrupt requests can be configured to be converted into DMA request signals. 
 Features of the Nested Vectored  Interrupt Controller (NVIC) 
 
  48 maskable peripheral interrupt channels (not including the 16 exception interrupts of Cortex-M3) 
   16 programmable interrupt priority levels (using 4-bit prioritized interrupts) 
   Facilitates low-latency exception and interrupt handling 
   Implements System Control Registers 
   Supports non-maskable interrupt (NMI) input 
 
The NVIC and the processor core  interface are closely coupled, providing mechanisms that enable 
low-latency interrupt processing and efficient processing  of late arriving interrupts. The NVIC maintains the 
nested interrupt information to enable tail chaining of interrupts. 
All interrupts are managed by the NVIC, including core exceptions. See Chapter 5: Exceptions and 
Chapter 8: Nested Vectored Interrupt Controller in the Cortex-M3 Technical Reference Manual from 
ARM for details on exceptions and NVIC. 
 
In the C ortex-M3 
T

echnical Reference Manual, all exception type: I
 RQ are defined as external interrupt 
inputs. In this manual, exception ty pe:IRQ are expressed as peripheral  interrupts. Peripheral interrupts 
include External Interrupt and NMI Control Unit interrupts from external pins and interrupts from 
peripheral resources within the LSI. 
 
  Interrupt Source Aggregation Function 
The interrupt request signals from each  peripheral resource are aggregated into 48 sources and input to the 
NVIC. Furthermore, the interrupt request signal from  the external NMIX pin is logically ORed with the 
hardware watchdog interrupt signal and input to the NVIC. 
  Peripheral Interrupt Request Batch Read Function 
The interrupt request batch read register allows the  interrupt request signals from the peripheral resources 
aggregated into a single interrupt request signal to  be read out at once. Reading this register makes it 
possible to check which interrupt request has occurred. However, the interrupt request flags cannot be 
cleared by using this function. Cl ear the interrupt request flags using the registers of each peripheral 
function. 
  Peripheral Interrupt Requests Output Selection Function 
DMA transfers can be started using the 32 interrupt requests from the peripheral functions. Use the 
DRQSEL register to select whethe r the interrupt request signals from each of the peripheral resources are 
output to the CPU or output to the DMAC. 
 
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2. Structure 
 
2. Structure 
This section shows the structure of the relationship between the interrupt controller and DMA 
transfer requests. 
 Interrupt Controller and DMA Transfer Request Block Diagram 
 
Figure 2-1 Interrupt controller and DMA transfer request block diagram 
 
R-bus
周辺
リソースR-bus 周辺
リソースPeripheral  resources
DMA transfer requests - 32 sources
DMAC
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
ch.6
ch.7
DMA transfer request 
clear signal
NVIC
Interrupt signal
(capable of DMA 
transfer)
- 32 sources
Interrupt signals (not capable of DMA transfer) + NMI
Interrupt source 
aggregation 
(logical OR)
Interrupt batch read 
(IRQMON reg.)Read Bus
Interrupts - 48 sources
＋NMI
Exceptions
CPU interrupt/DMA transfer 
allocation 
(output selector)
DRQSEL reg.
Exceptions - 15 sources (excluding NMI)
MFS ch. 0 
to 7
receive 
stop
Transfer request clear  generator
Bus
Cortex-M3
DMA transfer ACK
  
 
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3. Exception and Interrupt Vectors 
 
3.  Exception and Interrupt Vectors 
This section shows a vector table of the exceptions and interrupts input to the NVIC. 
Table 3-1 Exception and interrupt vectors Ve c t o r   No.  IRQ 
No.  Exception and Interrupt Source  Ve c t o r
Offset
0 -  Initial SP Value  0x00 
1 - Reset  0x04 
2 - Non-Maskable Interrupt (NMI) / Hardware Watchdog Timer  0x08 
3 - Hard Fault  0x0C
4 - Memory Management  0x10 
5 - Bus Fault  0x14 
6 - Usage Fault  0x18 
7-10 - Reserved  0x1C - 
0x2B
11  - SVCall (Supervisor Call)  0x2C
12 - Debug Monitor  0x30 
13 - Reserved  0x34 
14 - PendSV  0x38 
15 - SysTick  0x3C
16 0 Anomalous Frequency Detection by Clock Supervisor (FCS)  0x40 
17 1 Software Watchdog Timer  0x44 
18 2 Low Voltage Detector (LVD)  0x48 
19 3 MFT unit0, unit1 Wave Form Generator / DTIF(Motor Emergency Stop)  0x4C
20 4 External Interrupt Request ch.0 to ch.7  0x50 
21 5 External Interrupt Request ch.8 to ch.15  0x54 
22 6 Dual Timer / Quadrature Position/Resolution Counter (QPRC) ch.0, ch.1  0x58 
23 7 Reception Interrupt Request of Mu lti-Function Serial Interface ch.0  0x5C
24 8 Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.0  0x60 
25 
9 Reception Interrupt Request of Multi- Function Serial Interface ch.1  0x64 
26 10 Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.1  0x68 
27 
11 Reception Interrupt Request of Mu lti-Function Serial Interface ch.2  0x6C
28 12 Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.2  0x70 
29 
13 Reception Interrupt Request of Multi- Function Serial Interface ch.3  0x74 
30 14 Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.3  0x78 
31 
15 Reception Interrupt Request of Mu lti-Function Serial Interface ch.4  0x7C
32 16 Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.4  0x80 
33 
17 Reception Interrupt Request of Multi- Function Serial Interface ch.5  0x84 
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3. Exception and Interrupt Vectors 
 
Ve c t o r  No.  IRQ 
No.  Exception and Interrupt Source  Ve c t o r
Offset
34 18  Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.5  0x88 
35 
19 Reception Interrupt Request of Mu lti-Function Serial Interface ch.6  0x8C
36 20 Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.6  0x90 
37 
21 Reception Interrupt Request of Multi- Function Serial Interface ch.7  0x94 
38 22 Transmission Interrupt Request and Status Interrupt Request of Multi-Function 
Serial Interface ch.7  0x98 
39 23 
PPG ch.0/2/4/8/10/12  0x9C
40 24 External Main OSC / External Sub OSC / Main PLL / PLL for USB 
/ Watch Counter  0xA0
41 
25 A/D Converter unit0  0xA4
42 26 A/D Converter unit1  0xA8
43 27 A/D Converter unit2  0xAC
44 28 MFT unit0, unit1 Free-run Timer  0xB0
45 29 MFT unit0, unit1 Input Capture  0xB4
46 30 MFT unit0, unit1 Output Compare  0xB8
47 31 Base Timer ch.0 to ch.7  0xBC
48 32 CAN ch.0  0xC0
49 33 CAN ch.1  0xC4
50 34 USB Function (DRQ of End Point 1 to 5)    *  0xC8
51 35 USB Function (DRQI of End Point 0, DRQO and each status) 
/ USB HOST (each status)    *  0xCC
52 36 
Reserved  0xD0
53 37 Reserved  0xD4
54 38 DMA Controller (DMAC) ch.0  0xD8
55 39 DMA Controller (DMAC) ch.1  0xDC
56 40 DMA Controller (DMAC) ch.2  0xE0 
57 41 DMA Controller (DMAC) ch.3  0xE4 
58 42 DMA Controller (DMAC) ch.4  0xE8 
59 43 DMA Controller (DMAC) ch.5  0xEC
60 44 DMA Controller (DMAC) ch.6  0xF0 
61 45 DMA Controller (DMAC) ch.7  0xF4 
62 46 Reserved  0xF8 
63 47 Reserved  0xFC
 
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3. Exception and Interrupt Vectors 
 
*: USB Interrupt Source 
Ve c t o r  No.  IRQ 
No.  USB Interrupt Source Flags 
50 
34 USB Function (DRQ of End Point 1 to 5)  DRQ (End Point 1 to 5) 
USB Function 
(DRQI of End Point 0, DRQO and each status) DRQI, DRQO, SPK, SUSP, 
SOF, BRST, CONF, WKUP 
51 35 
USB HOST (each status)  DIRQ, URIRQ, RWKIRQ, 
CNNIRQ, SOFIRQ, CMPIRQ 
  The priorities of the exceptions for vectors no. 4 to 15  can be configured using the System Handler Priority 
Registers (address 0xE000ED18, 0xE000ED1C, 0xE000ED20) built into the NVIC. The priorities of the 
peripheral interrupts for vectors no. 16 and after can be configured using the 
Interrupt Priority Registers 
(address 0xE000E400 to 0xE000E42C) built into the NVIC. 
The sources of the interrupts for v ectors no. 2 and no. 16 to no. 63 ca n be checked using the batch read 
register. See NVIC in the Technical Reference Manual for details on the other exceptions and interrupts. 
Furthermore, for the interrupts of vectors no. 2 and no. 16 to no. 63, the sources that are batch read may be a 
signal that multiple interrupt sources are logical  OR’ed within each of the peripheral macros. See the 
descriptions of each of the peripher al resource interrupts for details. 
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4. Registers 
 
4. Registers 
This section explains the DMA transfer request selection register and the interrupt request 
batch read register. 
 DMA transfer request selection register  and interrupt request batch read 
register list 
Abbreviation Register  Name See 
DRQSEL DMA Transfer Request Selection Register  4.1 
EXC02MON EXC02 Batch Read Register  4.2 
IRQ00MON IRQ00 Batch Read Register  4.3 
IRQ01MON IRQ01 Batch Read Register  4.4 
IRQ02MON IRQ02 Batch Read Register  4.5 
IRQ03MON IRQ03 Batch Read Register  4.6 
IRQ04MON IRQ04 Batch Read Register  4.7 
IRQ05MON IRQ05 Batch Read Register  4.7 
IRQ06MON IRQ06 Batch Read Register  4.8 
IRQ07MON IRQ07 Batch Read Register  4.9 
IRQ08MON IRQ08 Batch Read Register  4.10 
IRQ09MON IRQ09 Batch Read Register  4.9 
IRQ10MON IRQ10 Batch Read Register  4.10 
IRQ11MON IRQ11 Batch Read Register  4.9 
IRQ12MON IRQ12 Batch Read Register  4.10 
IRQ13MON IRQ13 Batch Read Register  4.9 
IRQ14MON IRQ14 Batch Read Register  4.10 
IRQ15MON IRQ15 Batch Read Register  4.9 
IRQ16MON IRQ16 Batch Read Register  4.10 
IRQ17MON IRQ17 Batch Read Register  4.9 
IRQ18MON IRQ18 Batch Read Register  4.10 
IRQ19MON IRQ19 Batch Read Register  4.9 
IRQ20MON IRQ20 Batch Read Register  4.10 
IRQ21MON IRQ21 Batch Read Register  4.9 
IRQ22MON IRQ22 Batch Read Register  4.10 
IRQ23MON IRQ23 Batch Read Register  4.11 
IRQ24MON IRQ24 Batch Read Register  4.12 
IRQ25MON IRQ25 Batch Read Register  4.13 
IRQ26MON IRQ26 Batch Read Register  4.13 
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4. Registers 
 
Abbreviation Register Name  See 
IRQ27MON IRQ27 Batch Read Register  4.13 
IRQ28MON IRQ28 Batch Read Register  4.14 
IRQ29MON IRQ29 Batch Read Register  4.15 
IRQ30MON IRQ30 Batch Read Register  4.16 
IRQ31MON IRQ31 Batch Read Register  4.17 
IRQ32MON IRQ32 Batch Read Register  4.18 
IRQ33MON IRQ33 Batch Read Register  4.18 
IRQ34MON IRQ34 Batch Read Register  4.19 
IRQ35MON IRQ35 Batch Read Register  4.20 
IRQ36MON IRQ36 Batch Read Register  4.21 
IRQ37MON IRQ37 Batch Read Register  4.21 
IRQ38MON IRQ38 Batch Read Register  4.22 
IRQ39MON IRQ39 Batch Read Register  4.22 
IRQ40MON IRQ40 Batch Read Register  4.22 
IRQ41MON IRQ41 Batch Read Register  4.22 
IRQ42MON IRQ42 Batch Read Register  4.22 
IRQ43MON IRQ43 Batch Read Register  4.22 
IRQ44MON IRQ44 Batch Read Register  4.22 
IRQ45MON IRQ45 Batch Read Register  4.22 
IRQ46MON IRQ46 Batch Read Register  4.23 
IRQ47MON IRQ47 Batch Read Register  4.23 
 
See Chapter 8: Nested Vectored Interrupt Controller in the Cortex-M3 Technical Reference Manual for 
details on the registers in the NVIC. 
 
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4. Registers 
 
4.1.  DMA Request Selection Register (DRQSEL) 
The DMA Request Selection Register (DRQSEL) selects whether interrupt signals that can 
start DMA transfers are output as interrupt requests to the CPU or output as transfer requests 
to the DMAC. If selected as a transfer request to the DMAC, the bit in the interrupt request 
batch read register (IRQxxMON, xx=00 to 47) that corresponds to the interrupt signal is 0. 
 
bit 31  0 
Field DRQSEL[31:0] 
Attribute R/W 
Initial  value  0x00000000 
 
 
[bit31:0] DRQSEL :   
bit no.  bit  Description 
0 The interrupt of the external interrupt ch.3 is output as a request to the CPU. 31 
1 The interrupt of the external interrupt ch. 3 is output as a transfer request to the DMAC. 
0 The interrupt of the external interrupt ch. 2 is output as a request to the CPU. 30 
1 The interrupt of the external interrupt ch. 2 is output as a transfer request to the DMAC. 
0 The interrupt of the external interrupt ch. 1 is output as a request to the CPU. 29 
1 The interrupt of the external interrupt ch. 1 is output as a transfer request to the DMAC. 
0 The interrupt of the external interrupt ch. 0 is output as a request to the CPU. 28 
1 The interrupt of the external interrupt ch. 0 is output as a transfer request to the DMAC. 
0 The transmission interrupt of the MFS ch. 7 is output as a request to the CPU. 
27 
1 The transmission interrupt of the MFS ch. 7 
is output as a transfer request to the 
DMAC. 
0  The reception interrupt of the MFS ch.  7 is output as a request to the CPU. 26 
1 The reception interrupt of the MFS ch. 7 is  output as a transfer request to the DMAC. 
0 The transmission interrupt of the MFS ch. 6 is output as a request to the CPU. 
25 
1 The transmission interrupt of the MFS ch. 6 
is output as a transfer request to the 
DMAC. 
0  The reception interrupt of the MFS ch.  6 is output as a request to the CPU. 24 
1 The reception interrupt of the MFS ch. 6 is  output as a transfer request to the DMAC. 
0 The transmission interrupt of the MFS ch. 5 is output as a request to the CPU. 
23 
1 The transmission interrupt of the MFS ch. 5 
is output as a transfer request to the 
DMAC. 
0  The reception interrupt of the MFS ch.  5 is output as a request to the CPU. 22 
1 The reception interrupt of the MFS ch. 5 is  output as a transfer request to the DMAC. 
0 The transmission interrupt of the MFS ch. 4 is output as a request to the CPU. 
21 
1 The transmission interrupt of the MFS ch. 4 
is output as a transfer request to the 
DMAC. 
0  The reception interrupt of the MFS ch.  4 is output as a request to the CPU. 20 
1 The reception interrupt of the MFS ch. 4 is  output as a transfer request to the DMAC. 
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4. Registers 
 
bit no.  bit Description 
0 The transmission interrupt of the MFS ch. 3 is output as a request to the CPU. 
19 
1 The transmission interrupt of the MFS ch. 3 
is output as a transfer request to the 
DMAC. 
0  The reception interrupt of the MFS ch.  3 is output as a request to the CPU. 18 
1 The reception interrupt of the MFS ch. 3 is  output as a transfer request to the DMAC. 
0 The transmission interrupt of the MFS ch. 2 is output as a request to the CPU. 
17 
1 The transmission interrupt of the MFS ch. 2 
is output as a transfer request to the 
DMAC. 
0  The reception interrupt of the MFS ch.  2 is output as a request to the CPU. 16 
1 The reception interrupt of the MFS ch. 2 is  output as a transfer request to the DMAC. 
0 The transmission interrupt of the MFS ch. 1 is output as a request to the CPU. 
15 
1 The transmission interrupt of the MFS ch. 1 
is output as a transfer request to the 
DMAC. 
0  The reception interrupt of the MFS ch.  1 is output as a request to the CPU. 14 
1 The reception interrupt of the MFS ch. 1 is  output as a transfer request to the DMAC. 
0 The transmission interrupt of the MFS ch. 0 is output as a request to the CPU. 
13 
1 The transmission interrupt of the MFS ch. 0 
is output as a transfer request to the 
DMAC. 
0  The reception interrupt of the MFS ch.  0 is output as a request to the CPU. 12 
1 The reception interrupt of the MFS ch. 0 is  output as a transfer request to the DMAC. 
0 The IRQ 0 interrupt of the base timer ch. 6 is output as a request to the CPU. 11 
1 The IRQ 0 interrupt of the base timer ch. 6 is output as a transfer request to the DMAC. 
0 The IRQ 0 interrupt of the base timer ch. 4 is output as a request to the CPU. 10 
1 The IRQ 0 interrupt of the base timer ch. 4 is output as a transfer request to the DMAC. 
0 The IRQ 0 interrupt of the base timer ch. 2 is output as a request to the CPU. 9 
1 The IRQ 0 interrupt of the base timer ch. 2 is output as a transfer request to the DMAC. 
0 The IRQ 0 interrupt of the base timer ch. 0 is output as a request to the CPU. 8 
1 The IRQ 0 interrupt of the base timer ch. 0 is output as a transfer request to the DMAC. 
0 The scan conversion interrupt of the A/D converter unit 2 is output as a request to the CPU.
7 
1 The scan conversion interrupt of the A/D converter unit 2 is output as a transfer request to 
the DMAC. 
0 
The scan conversion interrupt of the A/D converter unit 1 is output as a request to the CPU.
6 
1 The scan conversion interrupt of the A/D converter unit 1 is output as a transfer request to 
the DMAC. 
0 
The scan conversion interrupt of the A/D converter unit 0 is output as a request to the CPU.
5 
1 The scan conversion interrupt of the A/D converter unit 0 is output as a transfer request to 
the DMAC. 
0 
The EP5 DRQ interrupt of the USB ch. 0 is output as a request to the CPU. 4 
1 The EP5 DRQ interrupt of the USB ch. 0 is output as a transfer request to the DMAC. 
0 The EP4 DRQ interrupt of the USB ch. 0 is output as a request to the CPU. 3 
1 The EP4 DRQ interrupt of the USB ch. 0 is output as a transfer request to the DMAC. 
0 The EP3 DRQ interrupt of the USB ch. 0 is output as a request to the CPU. 2 
1 The EP3 DRQ interrupt of the USB ch. 0 is output as a transfer request to the DMAC. 
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