Fujitsu Series 3 Manual
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4. CAN Registers 4.5.2. CAN New Data Registers 1, 2 (NEWDT1, NEWDT2) The CAN New Data Register indicates the NewDat bit of all message objects. This register checks which message object data is updated by reading the NewDat bit. Register configuration - CAN New Data Register 2 (High-order byte) bit 15 14 13 12 11 10 9 8 Field NewDat32-25 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN New Data Register 2 (Low-order byte) bit 7 6 5 4 3 2 1 0 Field NewDat24-17 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN New Data Register 1 (High-order byte) bit 15 14 13 12 11 10 9 8 Field NewDat16-9 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN New Data Register 1 (Low-order byte) bit 7 6 5 4 3 2 1 0 Field NewDat8-1 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 Register functions NewDat32-1: Data update bit Bit Function 0 Indicates that no valid data resides. 1 Indicates that valid data resides. The following shows conditions to set or reset the NewDat bit. Setting conditions Set 1 to the WR/RD bit of the IFx Command Mask Register, and 1 to the Control bit, and 1 to the NewDat bit of the IFx Message Control Register. Then write data to the IFx Command Request Register to set the NewDat bi t to a specific message object. The NewDat bit is set by receiving a data frame that passed through the acceptance filter. If the Dir bit is 1, the RmtEN bit is 0, and the UMask bit is 1, the NewDat bit is set by receiving a remote frame that passed through the acceptance filter. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1255 MB9Axxx/MB9Bxxx Series
4. CAN Registers Resetting conditions Set 0 to the WR/RD bit of the IFx Command Mask Register and 1 to the NewDat bit, and write data to the IFx Command Request Register to re set the NewDat bit of a specific message object. Set 1 to the WR/RD bit of the IFx Command Mask Register, and 1 to the Control bit, and 0 to the NewDat bit of the IFx Message Control Register. Then write data to the IFx Command Request Register to reset the NewDat bit of a specific message object. The NewDat bit is reset after data has been transf erred to the transmission shift register (internal register). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1256 MB9Axxx/MB9Bxxx Series
4. CAN Registers 4.5.3. CAN Interrupt Pending Registers 1, 2 (INTPND1, INTPND2) The CAN Interrupt Pending Register indicates the IntPnd bit of all message objects. This register checks which message object is pending for interrupt by reading the IntPnd bit. Register configuration - CAN Interrupt Pending Register 2 (High-order byte) bit 15 14 13 12 11 10 9 8 Field IntPnd32-25 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN Interrupt Pending Register 2 (Low-order byte) bit 7 6 5 4 3 2 1 0 Field IntPnd24-17 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN Interrupt Pending Register 1 (High-order byte) bit 15 14 13 12 11 10 9 8 Field IntPnd16-9 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN Interrupt Pending Register 1 (Low-order byte) bit 7 6 5 4 3 2 1 0 Field IntPnd8-1 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 Register functions IntPnd32-1: Interrupt pending bit Bit Function 0 No interrupt cause is detected. 1 An interrupt cause is detected. The following shows conditions to set or reset the IntPnd bit. Setting conditions If the TxIE bit is set to 1, the IntPnd bit is set when frame transmission has been completed normally. If the RxIE bit is set to 1, the IntPnd bit is se t when a frame that passed through the acceptance filter was received normally. Set 1 to the WR/RD bit of the IFx Command Mask Register, and 1 to the Control bit, and 1 to the IntPnd bit of the IFx Message Control Register. Then write data to the IFx Command Request Register to set the IntPnd b it of a specific message object. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1257 MB9Axxx/MB9Bxxx Series
4. CAN Registers Resetting conditions Set 0 to the WR/RD bit of the IFx Command Mask Re gister and 1 to the CIP bit, and write data to the IFx Command Request Register to reset th e IntPnd bit of a specific message object. Set 1 to the WR/RD bit of the IFx Command Mask Register, and 1 to the Control bit, and 0 to the IntPnd bit of the IFx Message Control Register. Then write data to the IFx Command Request Register to reset the IntPnd bit of a specific message object. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1258 MB9Axxx/MB9Bxxx Series
4. CAN Registers FUJITSU SEMICONDUCTOR LIMITED CHAPTER: CAN Controller FUJITSU SEMICONDUCTOR CONFIDENTIAL 68 4.5.4. CAN Message Valid Registers 1, 2 (MSGVAL1, MSGVAL2) The CAN Message Valid Register indicates the MsgVal bit of all message objects. This register checks which message object is valid by reading the MsgVal bit. Register configuration - CAN Message Valid Register 2 (High-order byte) bit 15 14 13 12 11 10 9 8 Field MsgVal32-25 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN Message Valid Register 2 (Low-order byte) bit 7 6 5 4 3 2 1 0 Field MsgVal24-17 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN Message Valid Register 1 (High-order byte) bit 15 14 13 12 11 10 9 8 Field MsgVal16-9 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN Message Valid Register 1 (Low-order byte) bit 7 6 5 4 3 2 1 0 Field MsgVal8-1 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 Register functions MsgVal32-1: Message valid bit Bit Function 0 Message objects are invalid. Disables message sending/receiving. 1 Message objects are valid. Enables message sending/receiving. The following shows conditions to set or reset the MsgVal bit. Setting conditions Set 1 to the WR/RD bit of the IFx Command Mask Register, and 1 to the Arb bit, and 1 to the MsgVal bit of the IFx Arbitration Register 2. Then write data to the IFx Command Request Register to set the MsgVal bit of a specific message object. Resetting conditions Set 1 to the WR/RD bit of the IFx Command Mask Register, and 1 to the Arb bit, and 0 to the MsgVal bit of the IFx Arbitration Register 2. Then write data to the IFx Command Request Register to reset the MsgVal bit of a specific message object. CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1259 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 1260 MB9Axxx/MB9Bxxx Series
1. CRC Overview Chapter: CRC (Cyclic Redundancy Check) This chapter explains the CRC functions. 1. CRC Overview 2. CRC Operations 3. CRC Registers CODE: FS15-E02.1 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 22: CRC \050Cyclic Redundancy Check\051 MN706-00002-1v0-E 1261 MB9Axxx/MB9Bxxx Series
1. CRC Overview 1. CRC Overview The CRC (Cyclic Redundancy Check) is an error detection system. The CRC code is a remainder after an input data string is divided by the pre-defined generator polynomial, assuming the input data string is a high order polynomial. Ordinarily, a data string is suffixed by a CRC code when being sent, and the receiv ed data is divided by a generator polynomial as described above. If the received data is dividable, it is judged to be correct. CRC functions This module enables the calculation in both CCITT CRC16 and IEEE-802.3 CRC32. In this module, the generator polynomial is fixed to the numeric values for those two modes; therefore, the CRC value based on other generator polynomials cannot be calculated. CCITT CRC16 generator polynomial: 0x1021 IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7 CRC configuration Figure 1-1 shows the CRC configuration. Figure 1-1 CRC configuration CRCCR 32-bit peripheral bus Bus I/F CRCINIT CRCINCRC Calculation CRCR Generator Polynomial [CRC16] 0x1021 [CRC32] 0x04C11DB7 CRCCR (CRC Control Register) Used to control CRC calculation. CRCINIT (CRC Initial Value Register) Used to specify the initial values for CRC calculation. CRCIN (Input Data Register) Used to set input data for CRC calculation. CRCR (CRC Register) Used to output the CRC calculation result. CRC Calculation A circuit to perform CRC calculation. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 22: CRC \050Cyclic Redundancy Check\051 MN706-00002-1v0-E 1262 MB9Axxx/MB9Bxxx Series
2. CRC Operations 2. CRC Operations This section provides an overview of CRC operations. CRC definition [CCITT CRC16 Standard] Generator polynomial 0x1021 (CRCCR. CRC32=0) Initial value 0xFFFF Final XOR value 0x0000 (CRCCR. FXOR=0) Bit order MSB First (CRCCR. LSBFST=0) Output bit order MSB First (CRCCR. CRCLSF=0) (The input-output byte order can be specified arbitrarily.) [IEEE-802.3 CRC32 Ethernet Standard] Generator polynomial 0x04C11DB7 (CRCCR. CRC32=1) Initial value 0xFFFFFFFF Final XOR value 0xFFFFFFFF (CRCCR. FXOR=1) Bit order LSB First (CRCCR. LSBFST=1) Output bit order LSB First (CRCCR. CRCLSF=1) (The input-output byte order can be specified arbitrarily.) Reset operations When resetting, the Initial Value Register (CRCINIT) and CRC Register (CRCR) are set to 0xFFFFFFFF. Other registers are cleared to 0. Initialization Initializing with CRCCR_INIT loads the value of the Initial Value Register to the CRC Register (CRCR). Processing byte and bit orders The following shows how to process byte and bit orders, using examples. Input the following one word to the CRC computing unit. 133.82.171.1 = 10000101 01010010 10101011 00000001 If the byte order is set to big endian (CRCCR_LTLEND=0) , the sending sequence in bytes is configured as shown below. 10000101 01010010 10101011 00000001 (1st) (2nd) (3rd) (4th) If the bit order is set to LSB First (CRCCR_LSBFST=1), the sending sequence in bits is configured as shown below. 10100001 01001010 11010101 10000000 (Head) (End) At CRCCR.CRCLTE=1, th e CRC result is rearranged in bytes with the 32-bit width in both CRC16 and CRC32. In pa rticu lar, in CRC16 mode, note that data is output to bit 31 to bit 16. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 22: CRC \050Cyclic Redundancy Check\051 MN706-00002-1v0-E 1263 MB9Axxx/MB9Bxxx Series
2. CRC Operations 2.1. CRC calculation sequence Figure 2-1 shows the CRC calculation sequence. In this section, it is assumed that the Initial Value Register (CRCINIT) setting, CRC16 or CRC32 mode selection (CRCCR.CRC32), and byte- or bit-order setting (CRCCR.LTLEND, CRCCR.LSBFST) have already been configured. (If the initial value can be set to ALLH, the Initial Value Register (CRCINIT) setting can be omitted.) Figure 2-1 CRC calculation sequence :CRC :DMA :CPU Initialization () CRC reading () Data writing () Data writing () Data writing () Start () CRC calculation () To perform initialization, write 1 to the initial value bit (CRCCR.INIT). The value of the Initial Value Register is loaded to the CRC Register (CRCR). To write input data, write to the Input Data Regist er (CRCIN). This then starts CRC calculation. If necessary, input data can be written continuously. Furt hermore, different bit widths can be used in a sequence to write input data. To obtain a CRC code, read the CRC Register (CRCR). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 22: CRC \050Cyclic Redundancy Check\051 MN706-00002-1v0-E 1264 MB9Axxx/MB9Bxxx Series