Fujitsu Series 3 Manual

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 4-2 Example clock setup procedure (Low-speed CR run mode -> Desired clock run 
mode) 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
No 
Select the main clock mode? 
_Yes 
No 
Main clock mode or PLL run mode 
Enable the PLL oscillation in the System Clock  Mode Control Register (SCM_CTL.PLLE=1). 
Set the master clock switch control bit of the  System Clock Mode Control Register 
(SCM_CTL.RCS) to a desired clock mode. 
Ye s  
Select the high-speed CR run mode?
Select the sub run mode? 
Ye s  
No 
Enable the main oscillation in the System Clock Mode Control Register (SCM_CTL.MOSCE=1).
PLL oscillation stable bit of the System Clock Mode 
Status Register (SCM_STR.PLRDY=1) 
Main clock oscillation stable bit of the System Clock Mode Status Register (SCM_STR.MORDY=1)  Start waiting for 
oscillation stability. 
Complete waiting for  oscillation stabilit
y. 
Main clock oscillation stable bit of the System Clock 
Mode Status Register (SCM_STR.MORDY=1)  Start waiting for 
oscillation stability. 
Complete waiting for  oscillation stability. 
Start waiting for 
oscillation stability. 
 
Check sub clock oscillation stable bit of the System 
Clock Mode Status Register (SCM_CTL.SORDY=1).  Complete waiting for oscillation stability.
 
Set the master clock switch control bit of the 
System Clock Mode Control Register 
(SCM_CTL.RCS) to a desired clock mode. 
Set the master clock switch control bit of the 
System Clock Mode Control Register 
(SCM_CTL.RCS) to a desired clock mode. 
Complete waiting for  oscillation stability.
Enable the sub oscillation in the System Clock 
Mode Control Register (SCM_CTL.SOSCE=1). 
with SCM_STR.RCM=SCM_CTL.RCS, changing  the mode to the selected clock mode. 
Low-speed 
CR r

un mode 
 
  Figure 4- 2 assu

mes that settings of the oscillation stabilization wait time, interrupts, PLL multiplication 
ratio and  b

us clock frequency division for each clock have been configured previously, and they are 
omitted from the flowchart. 
   In the sub clock mode/sub CR clock mode, the main clock(CLKMO), high-speed CR(CLKHC), PLL 
clock(CLKPLL) is stopped by hardware. So CLKM O/CLKHC/CLKPLL does not start oscillation only 
setting oscillation enable bit=1. These oscillations  will start by changing the SCM_CTL.RCS bit from 
sub clock mode/sub CR clock mode with setting oscillation enable bit=1. 
   If the main/sub oscillation stabilization wait times are short and the oscillation stabilization wait times 
run out before oscillators stabilize, reset may be applied by the clock supervisor function. 
 
 
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5.  Clock Generation Unit Register List 
This section provides clock generation register list. 
 Clock generation unit register list 
 
Abbreviation Register  name See 
SCM_CTL System Clock Mode Control Register  5.1 
SCM_STR System Clock Mode Status Register  5.2 
BSC_PSR Base Clock Prescaler Register  5.3 
APBC0_PSR APB0 Prescaler Register  5.4 
APBC1_PSR APB1 Prescaler Register  5.5 
APBC2_PSR APB2 Prescaler Register  5.6 
SWC_PSR SW-WDGT Clock Prescaler Register  5.7 
TTC_PSR Trace Clock Prescaler Register  5.8 
CSW_TMR Clock Stabilization Wait Time Register  5.9 
PSW_TMR PLL Clock Stabilization Wait Time Setup Register  5.10 
PLL_CTL1 PLL Control Register 1  5.11 
PLL_CTL2 PLL Control Register 2  5.12 
DBWDT_CTL Debug Break Watchdog Timer Control Register  5.13 
INT_ENR Interrupt Enable Register  5.14 
INT_STR Interrupt Status Register  5.15 
INT_CLR Interrupt Clear Register  5.16 
 
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5.1.  System Clock Mode Control Register (SCM_CTL) 
The SCM_CTL selects the master clock and enables/disables the clock oscillation. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field RCS[2:0]  PLLE SOSCE Reserved  MOSCE Reserved
Initial value   3b000   1b0  1b0  1b0  
Attribute  R/W   R/W R/W  - R/W  - 
 Register functions 
[bit 7:5] RCS: Master clock switch control bits 
Bit 7  Bit 6Bit 5  Description 
0 0 0 Internal high-speed CR oscillation clock [Initial value] 
0 0 1  Main oscillation clock 
0 1 0 PLL oscillation clock 
0 1 1 Setting disabled 
1 0 0 Internal low-speed CR oscillation clock 
1 0 1  Sub oscillation clock 
1 1 0 Setting disabled 
1 1 1 Setting disabled 
 
[bit 4] PLLE: PLL oscillation enable bit 
Bit Description 
0  Disables PLL oscillation [Initial value] 
1 Enables PLL oscillation 
 
[bit 3] SOSCE: Sub clock oscillation enable bit 
Bit Description 
0  Disables sub oscillation [Initial value] 
1 Enables sub oscillation 
 
[bit 2] res: Reserved bit  0 is read from this bit. 
Set this bit to 0 when writing. 
[bit 1] MOSCE: Main clock oscillation enable bit.   
Bit Description 
0  Disables main oscillation [Initial value] 
1 Enables main oscillation 
 
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[bit 0] RES: Reserved bit 0 is read from this bit. 
Set this bit to 0 when writing. 
 
  This reg i

ster is not initialized by software reset. 
   When you ch an

ge the clock mode, you should set the enable bit to transition for desired clock oscillation. 
Then, you can change the the System Clock Mode Control Register (SCM_CTL.RCS). 
 
 
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5.2.  System Clock Mode Status Register (SCM_STR) 
The SCM_STR indicates a clock selected for the master clock and a waiting state for clock 
oscillation stability. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field RCM[2:0]  PLRDYSORDYReserved  MORDY Reserved
Initial value   3b000   1b0  1b0 - 1b0 - 
Attribute   R   R  R - R - 
 Register functions 
[bit 7:5] RCM2 to RCM0: Master clock selection bits 
Bit 7  Bit 6Bit 5  Description 
0 0 0 Internal high-speed CR oscillation clock [Initial value] 
0 0 1  Main oscillation clock 
0 1 0 PLL oscillation clock 
0 1 1 Reserve 
1 0 0 Internal low-speed CR oscillation clock 
1 0 1  Sub oscillation clock 
1 1 0 Reserve 
1 1 1 Reserve 
 
[bit 4] PLRDY: PLL oscillation stable bit 
Bit Description 
0  In a stabilization wait or an oscillation stop state [Initial value] 
1 In a stable state 
 
[bit 3] SORDY: Sub clock oscillation stable bit 
Bit Description 
0  In a stabilization wait or an oscillation stop state [Initial value] 
1 In a stable state 
 
[bit 2] RES: Reserved bit  0 is read from this bit. 
 
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[bit 1] MORDY: Main clock oscillation stable bit 
Bit Description 
0 In a stabilization wait or an oscillation stop state [Initial value] 
1 In a stable state 
 
[bit 0] RES: Reserved bit  0 is read from this bit. 
 
 
This reg i

ster is not initialized by software reset. 
  
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5.3.  Base Clock Prescaler Register (BSC_PSR) 
The BSC_PSR sets the frequency division ratio of the base clock. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  BSR 
Initial value    -     3b000  
Attribute     -     R/W  
 Register functions 
[bit 7:3] RES: Reserved bits 
0b00000 is read  from these bits. 
Set these bits to 0b00000 when writing. 
[bit 2:0] BSR: Base clock frequency division ratio setting bit 
Bit 2  Bit 1Bit 0  Description 
0 0 0 1/1 [Initial value] 
0 0 1  1/2 
0 1 0 1/3 
0 1 1 1/4 
1 0 0 1/6 
1 0 1 1/8 
1 1 0 1/16 
1 1 1 Reserved 
 
 
This reg i

ster is not initialized by software reset. 
  
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5.4.  APB0 Prescaler Register (APBC0_PSR) 
The APBC0_PSR sets the APB0 bus clock frequency division. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  APBC0 
Initial value - 2b00 
Attribute -  R/W 
 Register functions 
[bit 7:2] RES: Reserved bits 
0b000000 is read from these bits. 
Set these bits to 0b000000 when writing. 
[bit 1:0] APBC0: APB0 bus clock frequency division ratio setting bit 
Bit 1  Bit 0 Description 
0 0 1/1 [Initial value] 
0 1 1/2 
1 0 1/4 
1 1 1/8 
 
 
This reg i

ster is not initialized by software reset. 
  
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5.5.  APB1 Prescaler Register (APBC1_PSR) 
The APBC1_PSR sets the APB1 bus clock frequency division. 
 Register configuration 
bit  7 6 5  4 3 2  1 0 
Field APBC1EN  Reserved APBC1RST Reserved  APBC1 
Initial value  1b1 -  1b0 -  2b00 
Attribute R/W - R/W  -  R/W 
 Register functions 
[bit 7] APBC1EN: APB1 clock enable bit 
Bit Description 
0 Disables PCLK1 output 
1  Enables PCLK1 output [Initial value] 
 
[bit 6:5] RES: Reserved bits  0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 4] APBC1RST: APB1 bus reset control bit 
Bit Description 
0  APB1 bus reset, inactive [Initial value] 
1 APB1 bus reset, active 
 
[bit 3:2] RES: Reserved bits  0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 1:0] APBC1: APB1 bus clock frequency division ratio setting bit 
Bit 1  Bit 0 Description 
0 0 1/1 [Initial value] 
0 1 1/2 
1 0 1/4 
1 1 1/8 
 
 
This reg i

ster is not initialized by software reset. 
  
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5.6.  APB2 Prescaler Register (APBC2_PSR) 
The APBC2_PSR sets the APB2 bus clock frequency division. 
 Register configuration 
bit  7 6 5  4 3 2  1 0 
Field APBC2EN  Reserved APBC2RST Reserved  APBC2 
Initial value  1b1 -  1b0 -  2b00 
Attribute R/W - R/W  -  R/W 
 Register functions 
[bit 7] APBC2EN: APB2 clock enable bit 
Bit Description 
0 Disables PCLK2 output 
1  Enables PCLK2 output [Initial value] 
 
[bit 6:5] RES: Reserved bits  0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 4] APBC2RST: APB2 bus reset control bit 
Bit Description 
0  APB2 bus reset, inactive [Initial value] 
1 APB2 bus reset, active 
 
[bit 3:2] RES: Reserved bits  0b00 is read from these bits. 
Set these bits to 0b00 when writing. 
[bit 1:0] APBC2: APB2 bus clock frequency division ratio setting bit 
Bit 1  Bit 0 Description 
0 0 1/1 [Initial value] 
0 1 1/2 
1 0 1/4 
1 1 1/8 
 
 
This reg i

ster is not initialized by software reset. 
  
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