Fujitsu Series 3 Manual

							 
1. Overview of Multifunction Timer 
 
CHAPTER: Multifunction Timer 
This chapter describes the multifunction timer unit. 
 
1.
 Overview of Multifunction Timer 
2. Configuration of Multifunction Timer 
3. Operations of Multifunction Timer 
4. Registers of Multifunction Timer 
5. Other Matters 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFMFT-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
495 
MB9Axxx/MB9Bxxx  Series  
						

							 
1. Overview of Multifunction Timer 
 
1.  Overview of Multifunction Timer 
The multifunction timer is a function block that enables three-phase motor control. In conjunction 
with PPG and ADC, it can provide a variety of motor controls. An overview of the multifunction 
timer is provided below. 
  Functions 
The multifunction timer has the following functions. 
  It can output PWM signals with any cycle/pulse length (PWM signal output function). 
   It can start PPG in synchronization with PWM signal output. It can superimpose PPG’s output signal on 
the PWM signal and output it (DC chopper waveform output function). 
   It can generate a non-overlap signal that maintains  the response time of the power transistor (dead time) 
from PWM signal output (dead timer function). 
   It can capture the timing of changing the input signal and its pulse width in synchronization with PWM 
signal output (Input capture function). 
   It can start ADC at any timing, in synchronization with PWM signal output (ADC start function). 
   It performs noise canceling to the emergency motor shutdown interrupt signal (DTTIX input signal). It 
can set freely the pin state at the time of motor shut down, when a valid signal input is detected (DTIF 
interrupt function). 
 
  Block Configuration 
The multifunction timer (1 unit) consists of the following function blocks. 
  Free-run Timer Unit  :  3ch. 
   Output Compare Unit  :  6ch.(2ch.×3unit) 
   Waveform Generator Unit  :  3ch. 
   Noise Canceler Unit  :  1ch. 
   Input Capture Unit  :  4ch.(2ch.×2unit) 
   ADC Start Compare Unit  :  3ch 
   ADC Start Trigger Selector Unit  :  3ch 
 
The multifunction timer is configured to enable one th ree-phase motor control, when 1 unit is used. Some 
models in this series contain multiple units of the multifunction timer, which are configured to support 
multiple three-phase motor controls. 
  Abbreviations 
In this chapter, the following abbreviations are used in explanations. 
  MFT : Multifunction Timer Unit 
   PPG  :  Programmable Pulse Generator Unit 
   FRT : Free-run Timer Unit 
   FRTS : Free-run Timer Selector 
   OCU : Output Compare Unit 
   WFG  :  Waveform Generator Unit 
   NZCL  :  Noise Canceler Unit 
   ICU : Input Capture Unit 
   ADCMP  :  ADC Start Compare Unit 
   ATSA  :  ADC Start Trigger Selector Unit 
 
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CHAPTER  15: Multifunction  Timer 
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2. Configuration of Multifunction Timer 
 
2.  Configuration of Multifunction Timer 
This chapter describes the configuration of the multifunction timer and the functions of each 
function block and I/O pin. 
 
2.1 Block Diagram of Multifunction Timer  
2.2  Description of Each Function Block  
2.3  I/O Pins of Multifunction Timer Unit 
 
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CHAPTER  15: Multifunction  Timer 
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2. Configuration of Multifunction Timer 
 
2.1.  Block Diagram of Multifunction Timer 
 Block Diagram 
Figure 2-1  shows the block diagram of the entire function timer. 
Figure 2-1 Block Diagram of Multifunction Timer 
 
3 ADC2 start trigger
from FRT0, FRT1,FRT2
3 ADC1 start trigger
from FRT0, FRT1,FRT2
RT0
RT1
RT2
RT3
RT4
RT5
3 PPG sig.
(from PPG )
3 ADC0 start trigger
from FRT0, FRT1,FRT2ADC0 scan start trigger
RTO0 output port
IC0 input port
ch.0
ch.10
from other
MFT-FRT
ch.1FRTS    
ch.2
ch.32
FRTS    
ch.3FRTS    
ch.4
ch.54
FRTS    
ch.5FRTS    
OCU
OCU
OCU
  WFG
ch.0FRTS    
ch.1FRTS    
ICU
NZCL
ch.2FRTS    
ch.3FRTS    
ICU
IC1 input port
IC2 input port
IC3 input port
RTO1 output port 
RTO2 output port
RTO3 output port
RTO4 output port
RTO5 output port
DTTIX
input port
FRTS    
FRTS    ch.0
FRTS    ch.1
FRTS    ch.2
FRTch.0
FRTch.1
FRTch.2
DTIF  Interrupt 
FRCK
input port
PCLK3 ADC start trigger from FRT0 to ADC0, ADC1, ADC2
3 ADC start trigger from FRT2 to ADC0, ADC1, ADC2
ATSAADCMP
to other 
MFT-FRT
ADC0 priority start trigger
ADC1 scan start trigger
ADC1 priority start trigger
ADC2 scan start trigger
ADC2 priority start trigger
 MFT
3 GATE sig. (to:PPG)SELSEL
2 Interrupt (FRT ch.0 )
2 Interrupt (FRT ch.1 )
2 Interrupt (FRT ch.2 )
6 Interrupt (OCU ch.0-5 )
3 Interrupt (WFG ch.10,32,54 )
4 Interrupt (ICU ch.0-3 )
3 ADC start trigger from FRT1 to ADC0, ADC1, ADC2
 
 
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CHAPTER  15: Multifunction  Timer 
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2. Configuration of Multifunction Timer 
 
2.2.  Description of Each Function Block 
 FRT: 3ch. 
  FRT is a timer function block that  outputs the reference counter value for the operation of each function 
block in MFT. 
   FRT consists of a clock pre-scaler ., 16-bit Up/Down counter, cycle se tting register (TCCP register) and 
controller.  Figure 2-2 shows the configuration of FRT. 
   The cl ock pre-
scal

er divides the peripheral clock (PCLK) signal in LSI to generate the operating clock 
for the 16-bit Up/Down counter. 
   The TCCP register sets the count cycle for the 16-b it Up/Down counter. It has a buffer register to 
change a cycle during count operation. 
   The 16-bit Up/Down counter performs Up-count or Down-count operation in the count cycle specified 
by the TCCP register in order to output a counter value. 
   The following processing can be achieved by instructin g the controller via CPU. 
   The division ratio of the cloc k pre-scaler can be selected. 
   The use of PCLK (internal clock) and FR CK (external clock) can be selected. 
   The count mode for the 16-bit Up/Down-counter can be  selected to specify whether to start or stop the 
count operation. 
   The buffer register function of the TCCP  register can be enabled or disabled. 
   Interrupt can be generated to CPU by detecting a cas e where the count value is set to 0x0000 or the 
peak value (= TCCP value) (two interrupt signals output per FRT1 channel). 
   AD conversion start signals can be generated to  each ADC by detecting a case where the count value 
is set to 0x0000 (three AD conversion start signals output per FRT1 channel). 
   Each MFT unit is in a 3-channel configuration with  three FRT’s, which can operate independently from 
one another. 
   Inside MFT, the output of the FRT counter value  is connected to OCU, ICU and ADCMP. These units 
have a circuit (FRTS) that selects FRT to be connect ed. Interlocked operation can be performed based on 
the output of the counter value of the selected FRT. A ll of the units can be interlocked by a single FRT, or 
2 or 3 groups can be formed as interlocked operational groups. 
 
Figure 2-2 Configuration of FRT 
 
  FRT
PCLKPre-scaler
FRCK
16bit UpDown
CounterCounter Output
TCCP reg.
Buf. reg.
Control circuit 
Clock
ADC0 start trigger
ADC1 start trigger
ADC2 start trigger
Zero detect Interrupt
Peak detect Interrupt
TCCP Write Data
TCCP Read Data
 
 
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CHAPTER  15: Multifunction  Timer 
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2. Configuration of Multifunction Timer 
 
 OCU: 6ch. (2ch. ×3) 
  OCU is a function block that generates and outputs PWM signals based on the counter value of FRT. The 
signal names of PWM signals output by OCU are RT0 to RT5. These signals are output to LSI’s external 
output pins via WFG. 
   OCU consists of FRTS, compare value store register (OCCP register) and controller. The basic unit is in 
a 2-channel configuration with  two sets of each circuit. Figure 2-3 shows the configuration of OCU. 
   FR TS is a circuit that selects th
e coun

ter va lue of FRT to be connected to OCU for use. 
   The OCCP register specifies the  timing of changing the PWM signal as the compare value for the FRT 
counter value. It has a buffer register to enable data to be written to the OCCP register 
asynchronously from FRT’s count operation. 
   The following processing can be achieved by instructing the controller from CPU. 
   FRT to be connected to OCU can be selected. 
   Whether to enable or disable OCU’s operation can be specified. 
   The output level of the RT0 to RT5 signal can be specified directly when OCU’s operation is disabled. 
   The output level of RT0 to RT5 signal changes, if OCU’s operation is enabled, the FRT counter value 
is compared with the value of the  compare value store register and then  it is detected that these values 
match. Signals with any cycle or pulse length can be  output by setting the value of the OCCP register 
beforehand. 
   The following modes are available for the change conditions of the RT0 to RT5 signal and can be 
selected: 
   Up-count, 1-change mode 
   Up-count, 2-change mode 
   Up/Down-count, Active  High  mode 
   Up/Down-count, Active  Low  mode 
   Interrupts can be generated to CPU, when it is det ected that the value of the OCCP register matches 
the FRT counter value. 
   Whether or not to use the buffer register of the OOCP register can be specified and the timing of 
transfer from the buffer register can be selected. 
   Each MFT contains three of these OCU’s and consists  of a total of 6 compare registers, 6 output signal 
pins and 6 interrupt outputs (2-channel × 3-unit configuration). 
 
Figure 2-3 Configuration of OCU 
 
FRTS    
 OCU
OCCP(0) reg.
Buf. reg.Control circuit 
RT(0) output
OCCP(0) Write Data
OCCP(0) Read Data
Match Interrupt (0)
FRTS    
OCCP(1) reg.
Buf. reg.
Control circuit 
RT(1) output
OCCP(1) Write Data
OCCP(1) Read Data
Match Interrupt (1)
FRT Counter input
FRT Counter input
 
 
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CHAPTER  15: Multifunction  Timer 
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2. Configuration of Multifunction Timer 
 
 WFG: 3ch 
  WFG is a function block that is located at the back of OCU and generates signal waveforms for motor 
control from the RT0 to RT5 and PPG signals (PPG is located outside the multifunction timer). 
   The signal outputs to LSI external pins from WFG are called RTO0 to RTO5. They are divided into 
blocks: the block that outputs RTO0 and RTO1 from RT0 and RT1; the block that outputs RTO2 and 
RTO3 from RT2 and RT3; and the block that outputs RTO4 and RTO5 from RT4 and RT5. They are 
called WFG ch.10, WFG ch.32 and WFG ch.54, respectively. 
   WFG consists of a clock pre-scal er, 16-bit timer (WFG timer), WFG  timer initial value register (WFTM 
register), waveform generator, PPG timer unit selectors and controller.  Figure 2-4 shows the 
co nfiguration of
 

WFG. 
   The clock pre-scaler divides the peripheral clock signal (PCLK) in LSI to generate the operating clock 
for the WFG timer.   
   The WFG timer is a timer circuit that counts the time set by the WFTM register and generates signal 
waveforms. In an operation mode that does not use a timer to generate a waveform, it can be used as 
a single reload timer, allowing interrupts to be  generated regularly to CPU. Each WFG timer has one 
WFG timer interrupt output. 
   The WFTM register can be used to set any count time to the WFG timer. 
   The waveform generator is a block that generates LSI external output signals through waveform 
generation processing based on the RT0 to RT5 signals from OCU, signals from PPG and the count 
state of the WFG timer. 
   The PPG timer unit selector is a circuit that selects  the PPG timer unit to be used by WFG. It selects 
the output destination of the instruction signal (GATE signal) for PPG activation and the PPG output 
signal. 
   The following processing can be achieved by instructing the controller from CPU. 
   The division ratio of the cloc k pre-scaler can be selected. 
   The following modes are available and ca n be selected for wave generation. 
   Through mode 
   RT-PPG mode 
   Timer-PPG mode 
   RT dead timer mode 
   PPG dead timer mode 
   GATE signal can be output to instruct PPG to start up. 
   Output polarity can be reversed in RT dead timer mode and PPG timer mode. 
 
Figure 2-4 Configuration of WFG 
 
WFG ch.10
PCLKPre-scalerWFG timer
Wave Generator
Clock
RTO0 output
WFTM reg.
WFG10 timer Interrupt
RTO1 output
Control Circuit
 WFG
WFG ch.32
WFG ch.54
PPG SelectorPPG Selector
WFG32 timer Interrupt
WFG54 timer Interrupt
RTO2 output
RTO3 output
RTO4 output
RTO5 output
RT0 input
RT1 input
RT2 input
RT3 input
RT4 input
RT5 input
3 PPG 
singnal input3 GATE singnal 
output
  
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CHAPTER  15: Multifunction  Timer 
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MB9Axxx/MB9Bxxx  Series  
						

							 
2. Configuration of Multifunction Timer 
 
 NZCL 
  NZCL is a function block that performs noise cancella tion to the external interrupt input signal (DTTIX 
signal) for emergency shutdown of the motor and generates DTIF interrupts to CPU. 
   NZCL consists of a noise canceller and controller. 
   It can be switched to the state of  the GPIO port which is also used for WFG’s external output signals 
(RTO0 to RTO5) using the selection function of the I/O port block while DTIF interrupt is being 
generated. Emergency shutdown of the motor can be performed by setting the I/O state of the GPIO port 
to the Motor Stop level. 
   Figure 2-5  shows the configuration of NZCL and I/O port selector. 
 
Figure 2-5 Configuration of NZCL and I/O Port Selector 
 
NZCL
Noise cancellerDTTIX
input portDTIF interrupt
RTO0 ～RTO5
GPIOI/O port
Selector
RTO0 ～RTO5
output portWFG
Interrupt contorller
OCU
MFT Motor Stop level
 
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CHAPTER  15: Multifunction  Timer 
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MB9Axxx/MB9Bxxx  Series  
						

							 
2. Configuration of Multifunction Timer 
 
 ICU: 4ch. (2ch. ×2) 
  ICU is a function block that captures the FRT count value and generates an interrupt to CPU when a 
valid edge is detected at an external input pin signal. 
   ICU consists of FRTS, edge detector, 16-bit capture register and control register. Its basic unit is in a 
2-channel configuration with  two sets of each circuit. Figure 2-6 shows the configuration of ICU. 
   FR TS is a circuit that selects th
e coun

ter valu e of the FRT to be connected to ICU for use. 
   The edge detector is a circuit that det ects the valid edge of the input signal. 
   The ICCP register captures the timing of changi ng the input signal as FRT’s count value. 
   The following processing can be achieved by instructing the controller from CPU. 
   FRT to be connected to ICU can be selected. 
   The valid edge of the input signal can be selected  from rising edge, falling edge and both edges. 
   Whether to enable or disable IC U’s operation can be specified. 
   An interrupt can be generated to CPU when the valid edge is detected and the capture operation is 
performed. 
   Each MFT contains 2 ICU’s and consists of a total of 4 external input pins and 4 capture registers 
(2-channel × 2-unit configuration). LSI external  input signals to ICU are called IC0 to IC3. 
   Some ICU input signals can be switched to LSI’s internal signals for use, other than LSI external pins, 
using the selection function of the I/O port block (see  2.3 I/O Pins of Multifunction Timer Unit  for 
m ore details). 
 
Figure 2-6 Configuration of ICU 
 
FRTS    
 ICU
Edge det.
ICCP(0)ICCP(0) Read data
IC(0)Dec. Interrupt (0)
FRT Counter input
Control circuit 
FRTS    
Edge det.
ICCP(1)ICCP(1) Read data
IC(1)Dec. Interrupt (1)
FRT Counter input
Control circuit 
 
 
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CHAPTER  15: Multifunction  Timer 
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2. Configuration of Multifunction Timer 
 
 ADCMP: 3ch. 
  ADCMP is a function block that generates AD conver sion start signals at any timing of FRT cycle. 
   ADCMP is in a 3-channel configuration with each corr esponding to one of the 3 units of ADC mounted. 
   ADCMP consists of FRTS, two 16-bit compare regi sters (ACCP register and ACCPDN register) and 
control register.  Figure 2-7 shows the configuration of ADCMP and ATSA. 
   FRTS is a circuit that selects th e coun

ter value of the FRT to be connected to ADCMP for use. 
   The ACCP register and ACCPDN regi ster specify the timing of starting AD conversion as the compare 
value of FRT’s counter value. Each has a buffer re gister so that writing to the ACCP register and 
ACCPDN register can be done asynchronously from FRT’s count operation. 
   The following processing can be achieved by instructing the controller from CPU. 
   FRT to be connected to ADCMP can be selected. 
   Whether to enable or disable ADCMP operation can be specified. 
   The timing of starting AD conversion can be  set with a specified FRT count direction. 
   Whether or not to use the ACCP register and ACCP DN’s buffer register can be specified and the 
timing of transferring from the bu ffer register can be selected. 
 ATSA: 3ch. 
  ATSA is a function block that selects and outputs ADC’s start signals based on the value of the control 
register.  
   ATSA consists of a logic OR circuit for AD start si gnals and a circuit that selects the AD start signals 
from ADCMP. 
   The following is processed. 
   Start signals from FRT to each ADC undergo logi c OR operation for each corresponding ADC  unit. 
   The above ADC start signal and other ADC start sign al from ADCMP are selected by register setting. 
   There are two types of ADC start  triggers: scan start triggers and priority start triggers. The 
configuration allows each to be selected and output. 
   ATSA is configured to support each start trigger  of three mounted ADC units. It outputs 6 ADC start 
signals. 
 
Figure 2-7 Configuration of ADCMP and ATSA 
 
ADCMP ADC2 start trigger
ADCMP ADC1 start trigger
ADC0 scan
start triggerFRTS    
 ADCMP ch.0
ACCP0 reg.
Buf. reg.Control 
circuit ACCP0 Write Data
ACCP0 Read Data
ACCPDN1 reg.
Buf. reg.ACCPDN0 Write Data
ACCPDN1 Read Data
FRT Counter input
 ADCMP
 ADCMP ch.1FRT Counter input
Write Read Data
FRT Counter input
Write Read Data
FRT0-ADC0 start trigger 
　 ATSA
FRT1-ADC0 start trigger FRT2-ADC0 start trigger 
 ADCMP ch.2
ADCMP ADC0 start trigger
FRT0-ADC1 start trigger FRT1-ADC1 start trigger FRT2-ADC1 start trigger 
FRT0-ADC2 start trigger FRT1-ADC2 start trigger FRT2-ADC2 start trigger 
ADC0 priority
start trigger
ADC1 scan
start trigger
ADC1 priority
start trigger
ADC2 scan
start trigger
ADC2 priority
start trigger
  
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
504 
MB9Axxx/MB9Bxxx  Series